since commit 12d1ad0c75 : update capstone include path ...
the generated capstone.pc is not working
so fix the includedir in capstone.pc to get github action working
Change-Id: I7767e181a74c73a7514eeb6293cd556a794dbfe9
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6969
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The device has compatible flash macro with STM32F1 family, reuse
stm32f1x driver code.
Detect non-ARM target - for simplicy test target type name 'riscv'
and the address has 32 bits.
In case of RISC-V CPU use simple chunked write algo - async algo
cannot be used as the core implemented in this device doesn't
allow memory access while running.
Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6704
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Replace deprecated commands 'mem2array' and 'array2mem' with
new Tcl commands 'read_memory' and 'write_memory'.
Change-Id: I116d995995396133ca782b14cce02bd1ab917a4e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6859
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* Move more smarts into the target algorithm code, and rewrite that in C
so it's easier to understand/maintain.
* Support >24-bit addresses.
* Check for errors.
Change-Id: I3b1a143589fe6defafb8f95820aa682acc9646e7
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6679
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The busy flag must be polled after each half-page write.
At low clock speeds, no issue is observed when the poll
is omitted, because the writes complete before the next
write begins. But at high clock speeds the subsequent
writes would overlap and cause the operation to fail.
The status polls are done on the target for efficiency,
since the half-pages are very small.
Change-Id: Ia1e9b4a6a71930549b3d84a902744ce6e596301b
Signed-off-by: Jimmy <nhminus@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5598
Tested-by: jenkins
Reviewed-by: Jelle De Vleeschouwer
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
The driver is in OpenOCD since 2007, but the USB VID/PID have
never been listed in udev rules.
Change-Id: I77df469929dd7f6b6483678c0e76f22c30a7614c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6563
Tested-by: jenkins
Add the 0x3754 PID used by some STLINK-V3 devices when MSD has been
disabled. This PID has been observed on a Nucleo-G431RB board.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Change-Id: Idb85874fa5a9dff5940bae7e95426a956693b976
Reviewed-on: https://review.openocd.org/c/openocd/+/6555
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
stm32l4_work_area struct is shared between the loader and stm32l4x flash driver
'*wp' and '*rp' pointers' size is 4 bytes each since stm32l4x devices have
32-bit processors.
however when used in openocd code, their size depends on the host
if the host is 32-bit, then the size is 4 bytes each.
if the host is 64-bit, then the size is 8 bytes each.
to avoid this size difference, change their types depending on the
usage (pointers for the loader, and 32-bit integers in openocd code).
Change-Id: I0a3df4bb4bf872b01cdb9357eb28307868d7d469
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6556
Tested-by: jenkins
Reviewed-by: Yestin Sun <sunyi0804@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
switching to C loader instead of the assembly version will enhance readability
will reduce the maintenance effort.
besides the switch to C loader, we added a new parameters to the loader
like flash_word_size and flash_sr_bsy_mask in order to support properly
STM32U5x and STM32G0Bx/G0Cx in dual-bank mode.
Change-Id: I24cafc2ba637a065593a0506eae787b21080a0ba
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6109
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Add support for ECP5 FPGA targets and board based on this chips:
Radiona ULX3S and Lambdaconcept ECPIX-5
Change-Id: I932fc6e2458cda7d63ac21579acddea5b53410bc
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6112
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Use a command group 'remote_bitbang' with subcommands instead of individual
commands with 'remote_bitbang_' prefix.
The old commands are still available for backward compatibility but
marked as deprecated.
Change-Id: I2692320f19c8a357112a365db6ca7e13cd6ad411
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6389
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
atoi used but stdlib.h wasn't included.
Also, include statements reordered alphabetically.
Change-Id: I7fcdbf3fa940a172204ec811399e1a7fdebdc979
Signed-off-by: Diego Herranz <diegoherranz@diegoherranz.com>
Reviewed-on: http://openocd.zylin.com/6312
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
All Altera USB Blaster devices require a dedicated line in the
udev rules, but some USB VID/PID present in interface and board
config file is missing in udev rules.
Add the missing Altera USB Blaster devices in udev rules.
While there, fix an incorrect pair VID/PID that are reported
swapped inside a comment.
Change-Id: I2d67e90b10db99ef2638405585859c1393456f65
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6102
Tested-by: jenkins
All ftdi devices require a dedicated line in the udev rules, but
some USB VID/PID present in interface and board config file is
missing in udev rules.
Add the missing ftdi devices in udev rules.
Change-Id: I850a4a95a2d4bb63b3fd09be803be8c23c4d6b49
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6101
Tested-by: jenkins
Commit 68e204f1e9 ("udev: Add rules for Ambiq Micro EVK's.") was
initially proposed as http://openocd.zylin.com/3429/ then replaced
by http://openocd.zylin.com/3980/
The initial proposal was for file '99-openocd.rules', in which
MODE="664" was the norm.
After merge of http://openocd.zylin.com/2804/ the new udev rules
in '60-openocd.rules' switched to MODE="660", but the evolution of
the above patch missed this change.
Switch udev rules of Ambiq Micro EVK's to MODE="660" and uniform
them to the rest of the file.
Change-Id: I4b4eea535184ee8569da3264bff4f1fafb5bce4d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 68e204f1e9 ("udev: Add rules for Ambiq Micro EVK's.")
Reviewed-on: http://openocd.zylin.com/6004
Tested-by: jenkins
And get rid of some warnings along the way.
Change-Id: I8fdbe1fa304276be6b0f25249b902b3576aa3793
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5987
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
- write speed up to 150 kByte/s on STM32F469I-disco (due to
SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI
with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in
dual 4-line mode or STM32H73BI-Disco in octal mode
- tested with STM32L476G-disco (64MBit flash, 3-byte addr),
STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and
STM32L476G-Disco (all 128Mbit flash, 3-byte addr),
STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)
STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)
STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)
STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)
- suitable cfg for Discovery boards included
- limited parsing of SFDP data if flash device not hardcoded
(tested only in single/quad mode as most devices either don't
support SFDP at all or have empty(!) SFDP memory)
- 'set' command for auto detection override (e. g. for EEPROMs)
- 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.)
- makefile for creation of binary loader files
- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg
- tcl/board/stm32f7discovery.cfg removed as name is ambiguous
(superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)
- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q
with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI
with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,
STM32H747I-Disco, STM32H750B-Disco
- read/verify/erase_check uses indirect read mode to work around silicon bug in
H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last
bytes causes debug interface to hang)
- octospi supported only in single/dual 1-line, 2-line, 4-line
and single 8-line modes, (not in hyper flash mode)
Requirements:
GPIOs must be initialized appropriately, and SPI flash chip be configured
appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip
specific, cf. included cfg files. The driver infers most parameters from
current setting in CR, CCR, ... registers.
Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4321
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
This change could be used within OpenOCD GitHub forks.
Once workflow actions are enabled in the GitHub project, this workflow
will be run automatically on each push into OpenOCD.
This workflow will provide a neutral build of openocd for win32, then
the package will be available for download in Actions section.
Note: the artifact will be deleted after 90 day (actual GitHub rules)
If the push is a tag, the generated package will be uploaded to release
pane under the corresponding release, and it will resides forever.
The built openocd enables libusb1, hidapi and libftdi adapters,
and could be extended to cover more adapters and Oses
PS: ./contrib/cross-build.sh updated to build libftdi from source like
libusb1 and hidapi.
Change-Id: I290c8aa14a12548e2dcb6a0eee456430ea44ab9f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5594
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Implementation largely taken from Nuvoton github
https://github.com/OpenNuvoton/OpenOCD-Nuvoton
Reset is still not fully compatible with OpenOCD framework.
Adapted to hidapi.
Change-Id: Ieb1791b1b7f0b444c15c9668f8f2bcf34975d48f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Zale Yu <cyyu@nuvoton.com>
Reviewed-on: http://openocd.zylin.com/5720
Tested-by: jenkins
Reviewed-by: Saravanan Sekar <saravanan@linumiz.com>
Reviewed-by: Marc Schink <dev@zapb.de>
Add support for Nu-Link1 over usb hidapi and config file.
The original work is fetched from Nuvoton github.
Code cleanup, fix merge conflicts, compile and runtime issues.
Switch the code from libusb to hidapi, being the device HID based.
Add documentation.
Merge fixes for multi-word memory read.
Reset is not fully compatible with openocd framework; currently
the target is reset and then halt at openocd start.
Change-Id: I9738de4e26783ba462ea3e39ec32069fd5bb7d94
Signed-off-by: Zale Yu <cyyu@nuvoton.com>
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5635
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
While there, replace s/return(0)/return 0/ that causes checkpatch
to fail.
Change-Id: I5ad54cffca629475563c471114a9f77301a9e4f8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5768
Tested-by: jenkins
Empty lines at end of text files are useless.
Remove them.
Change-Id: I4efbd9af5be7e16213dcc7cb95de936ecde2fcef
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5173
Tested-by: jenkins
If watchdog is enabled, there's no way we can disable it while the flashing firmware
is running. (Halt disables it, but software reset doesn't.) So let's have the flashing
firmware refresh the watchdog regularly, in case it has been enabled by previously
running software. Failure to do so could lead to a watchdog reset in the middle of
the chip bieng programmed.
Change-Id: I79d41593948aae0080480e891552e1c2ee3ccbd0
Signed-off-by: Aurélien Martin <martaurel@gmail.com>
Reviewed-on: http://openocd.zylin.com/5266
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The XDS110 supports alternate configurations, each of which has
a unique vid/pid:
0451/bef3 -- Standard (legacy) configuration
0451/bef4 -- Drag-n-Drop configuration
1cbe/02a5 -- CMSIS-DAP 2.0 on BULK interface configuration
It's not important to OpenOCD what the differences are except
that OpenOCD needs to know how to connect using the different
vid/pids and, in the case of the last one, use a different
interface for the debug connection.
Updated the XDS110 source to search for all possible
configurations, and updated the udev rules file to enable
user access to the alternate configuraitons.
For the curious, you can download the latest XDS emupack from
software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html
Install to an empty directory, and documentation for the
XDS110 is located in the .../ccs_base/common/uscif/xds110
of the installation.
Updated for comments in code review. Changed const variable
names to lower case. Reworked interface/endpoint setting
to use arrays suggestion.
Change-Id: Icc9d11c6618f43d87ae8171c78ebf238800d3ac2
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5494
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Flash module of STM32G0/G4 family is quite similar to the one of
STM32L4, so only minor changes are required, in particular
adaption of flash loader to Cortex-M0. Register addresses
passed to flash loader to simplify integration of L5.
Added re-probe after option byte load.
Added flash size override via cfg file.
WRPxxR mask now based on max. number of pages instead of fixed 0xFF,
as G4 devices fill up unused bits with '1'.
Sizes in stm32l4_probe changed to multiples of 1kB.
Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE.
Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB.
This handling isn't optimal as the bank size includes the
size of the gap. WB not tested.
Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4807
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Adopted only fast algorithm for flash programming:
- write_word and write_byte methods have been removed.
- start and end write alignments have been defined.
Moved flash controller registers offsets in a common file
shared with the flash algorithm.
- the flash base address is passed to the flash algorithm
as a parameter.
Removed unused functions
Change-Id: I80aeab3994e477044bbcf02e66d9525dae0cb491
Signed-off-by: luca vinci <luca.vinci@st.com>
Reviewed-on: http://openocd.zylin.com/5393
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Michele Sardo <msmttchr@gmail.com>
this new device has the following features:
- single core cortex-M7
- 2MB flash - dual bank
- page size 8k
- write protection grouped by 4 sectors
- write block size 128 bits (16 bytes)
the bit definition of FLASH_CR is different than STM32H74x,
that's why we introduced a helper to compute the FLASH_CR value
Change-Id: I4da10cde8dd215b1b0f2645f0efdba9d198038d1
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5441
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Some text file is missing newline at EOF.
Add it.
Change-Id: Ieebc790096f40961283c644642e56fde975e957f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5167
Tested-by: jenkins
Fix comment of tested errors in asm src.
List all relevant errors in FLASH_ERROR mask: FLASH_PROGERR was missing
and any trial to re-program already programmed double word ended up
in the error bit held uncleared and flash write permanetly repeating
the error message until reset.
Lock the bank also after unsuccesfull write_block run.
Set async target algo block size to size of double word.
Remove warning in case of write_block success. In case of error
use LOG_ERROR instead of warning.
Change-Id: Ibf6d5e306a4c2eaa43de67d636b4902c737f02f3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5360
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Add driver for the SH QSPI controller. This SPI controller is often
connected to the boot SPI NOR flash on R-Car Gen2 platforms.
Add the following two lines to board TCL file to bind the driver on
R-Car Gen2 SoC and make SRAM work area available:
flash bank flash0 sh_qspi 0xe6b10000 0 0 0 ${_TARGETNAME}0 cs0
${_TARGETNAME}0 configure -work-area-phys 0xe6300000 -work-area-virt 0xe6300000 -work-area-size 0x10000 -work-area-backup 0
To install mainline U-Boot on the board, use the following procedure:
proc update_uboot {} {
# SPL
flash erase_sector 0 0x0 0x0
flash write_bank 0 /u-boot/spl/u-boot-spl.bin 0x0
# U-Boot
flash erase_sector 0 0x5 0x6
flash write_bank 0 /u-boot/u-boot.img 0x140000
}
Change-Id: Ief22f61e93bcabae37f6e371156dece6c4be3459
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
---
V2: - Add Makefile and linker script for the SH QSPI IO algorithm
- Include the algorithm code instead of hard-coding it
Reviewed-on: http://openocd.zylin.com/5143
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Add these methods such that the OpenOcd class can also be used outside
of a 'with' statement.
Change-Id: I927c93fff2dc05cc74daa56360a7262e736a639f
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/5189
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4
The second core creation is only done when
* DUAL_CORE variable is set to true
* non HLA interface is used
A second check for the second core existence is done in cpu1 examine-end
Once the second core is detected it gets examined.
Furthermore, the script provides a configurable CTI usage in order to halt
the cores simultaneously.
Tested on Rev X and V devices.
PS: the indentation was a mix of spaces and tabs, all changed to tabs.
Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5130
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tarek BOCHKATI
Tomas Vanek
Marc Schink
Tim Newsome
Jimmy
Antonio Borneo
Andreas Sandberg
Wealian Liao
Oleksij Rempel
Ranjith Chandran
Diego Herranz
Andreas Fritiofson
Jiri Kastner
Andrew Wesie
Paul Fertser
Tarek BOCHKATI
Andreas Bolsch
Zale Yu
Alistair Francis
Aurélien Martin
Edward Fewell
luca vinci
Marek Vasut
Marc Schink
Ake Rehnman