flash/stm32h7x: add support of STM32H7Ax/H7Bx devices
this new device has the following features:
- single core cortex-M7
- 2MB flash - dual bank
- page size 8k
- write protection grouped by 4 sectors
- write block size 128 bits (16 bytes)
the bit definition of FLASH_CR is different than STM32H74x,
that's why we introduced a helper to compute the FLASH_CR value
Change-Id: I4da10cde8dd215b1b0f2645f0efdba9d198038d1
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5441
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tarek BOCHKATI
Tomas Vanek
parent
98ea23a7ff
commit
0b7eca1769
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@ -25,29 +25,35 @@
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* Code limitations:
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* The workarea must have size multiple of 4 bytes, since R/W
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* operations are all at 32 bits.
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* The workarea must be big enough to contain 32 bytes of data,
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* thus the minimum size is (rp, wp, data) = 4 + 4 + 32 = 40 bytes.
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* The workarea must be big enough to contain rp, wp and data, thus the minumum
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* workarea size is: min_wa_size = sizeof(rp, wp, data) = 4 + 4 + sizeof(data).
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* - for 0x450 devices: sizeof(data) = 32 bytes, thus min_wa_size = 40 bytes.
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* - for 0x480 devices: sizeof(data) = 16 bytes, thus min_wa_size = 24 bytes.
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* To benefit from concurrent host write-to-buffer and target
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* write-to-flash, the workarea must be way bigger than the minimum.
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*/
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*
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* To avoid confusions the write word size is got from .block_size member of
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* struct stm32h7x_part_info defined in stm32h7x.c
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*/
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/*
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* Params :
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* r0 = workarea start, status (out)
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* r1 = workarea end
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* r2 = target address
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* r3 = count (256 bit words)
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* r4 = flash reg base
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* r3 = count (of write words)
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* r4 = size of write word
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* r5 = flash reg base
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*
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* Clobbered:
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* r5 - rp
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* r6 - wp, status, tmp
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* r7 - loop index, tmp
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* r6 - rp
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* r7 - wp, status, tmp
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* r8 - loop index, tmp
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*/
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#define STM32_FLASH_CR_OFFSET 0x0C /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
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#define STM32_CR_PROG 0x00000032 /* PSIZE64 | PG */
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#define STM32_CR_PROG 0x00000002 /* PG */
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#define STM32_SR_QW_MASK 0x00000004 /* QW */
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#define STM32_SR_ERROR_MASK 0x07ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
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| INCERR | STRBERR | PGSERR | WRPERR */
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@ -55,54 +61,55 @@
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.thumb_func
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.global _start
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_start:
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ldr r5, [r0, #4] /* read rp */
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ldr r6, [r0, #4] /* read rp */
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wait_fifo:
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ldr r6, [r0, #0] /* read wp */
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cbz r6, exit /* abort if wp == 0, status = 0 */
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subs r6, r6, r5 /* number of bytes available for read in r6 */
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ldr r7, [r0, #0] /* read wp */
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cbz r7, exit /* abort if wp == 0, status = 0 */
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subs r7, r7, r6 /* number of bytes available for read in r7 */
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ittt mi /* if wrapped around */
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addmi r6, r1 /* add size of buffer */
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submi r6, r0
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submi r6, #8
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cmp r6, #32 /* wait until 32 bytes are available */
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addmi r7, r1 /* add size of buffer */
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submi r7, r0
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submi r7, #8
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cmp r7, r4 /* wait until data buffer is full */
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bcc wait_fifo
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mov r6, #STM32_CR_PROG
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str r6, [r4, #STM32_FLASH_CR_OFFSET]
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mov r7, #STM32_CR_PROG
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str r7, [r5, #STM32_FLASH_CR_OFFSET]
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mov r7, #8 /* program by 8 words = 32 bytes */
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mov r8, #4
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udiv r8, r4, r8 /* number of words is size of write word devided by 4*/
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write_flash:
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dsb
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ldr r6, [r5], #0x04 /* read one word from src, increment ptr */
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str r6, [r2], #0x04 /* write one word to dst, increment ptr */
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ldr r7, [r6], #0x04 /* read one word from src, increment ptr */
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str r7, [r2], #0x04 /* write one word to dst, increment ptr */
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dsb
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cmp r5, r1 /* if rp >= end of buffer ... */
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cmp r6, r1 /* if rp >= end of buffer ... */
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it cs
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addcs r5, r0, #8 /* ... then wrap at buffer start */
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subs r7, r7, #1 /* decrement loop index */
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addcs r6, r0, #8 /* ... then wrap at buffer start */
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subs r8, r8, #1 /* decrement loop index */
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bne write_flash /* loop if not done */
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busy:
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ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
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tst r6, #STM32_SR_QW_MASK
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ldr r7, [r5, #STM32_FLASH_SR_OFFSET]
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tst r7, #STM32_SR_QW_MASK
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bne busy /* operation in progress, wait ... */
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ldr r7, =STM32_SR_ERROR_MASK
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tst r6, r7
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ldr r8, =STM32_SR_ERROR_MASK
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tst r7, r8
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bne error /* fail... */
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str r5, [r0, #4] /* store rp */
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str r6, [r0, #4] /* store rp */
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subs r3, r3, #1 /* decrement count */
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bne wait_fifo /* loop if not done */
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b exit
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error:
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movs r7, #0
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str r7, [r0, #4] /* set rp = 0 on error */
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movs r8, #0
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str r8, [r0, #4] /* set rp = 0 on error */
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exit:
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mov r0, r6 /* return status in r0 */
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mov r0, r7 /* return status in r0 */
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bkpt #0x00
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.pool
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@ -1,7 +1,8 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x45,0x68,0x06,0x68,0x36,0xb3,0x76,0x1b,0x42,0xbf,0x76,0x18,0x36,0x1a,0x08,0x3e,
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0x20,0x2e,0xf6,0xd3,0x4f,0xf0,0x32,0x06,0xe6,0x60,0x4f,0xf0,0x08,0x07,0xbf,0xf3,
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0x4f,0x8f,0x55,0xf8,0x04,0x6b,0x42,0xf8,0x04,0x6b,0xbf,0xf3,0x4f,0x8f,0x8d,0x42,
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0x28,0xbf,0x00,0xf1,0x08,0x05,0x01,0x3f,0xf1,0xd1,0x26,0x69,0x16,0xf0,0x04,0x0f,
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0xfb,0xd1,0x05,0x4f,0x3e,0x42,0x03,0xd1,0x45,0x60,0x01,0x3b,0xd9,0xd1,0x01,0xe0,
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0x00,0x27,0x47,0x60,0x30,0x46,0x00,0xbe,0x00,0x00,0xee,0x07,
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0x46,0x68,0x07,0x68,0x6f,0xb3,0xbf,0x1b,0x42,0xbf,0x7f,0x18,0x3f,0x1a,0x08,0x3f,
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0xa7,0x42,0xf6,0xd3,0x4f,0xf0,0x02,0x07,0xef,0x60,0x4f,0xf0,0x04,0x08,0xb4,0xfb,
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0xf8,0xf8,0xbf,0xf3,0x4f,0x8f,0x56,0xf8,0x04,0x7b,0x42,0xf8,0x04,0x7b,0xbf,0xf3,
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0x4f,0x8f,0x8e,0x42,0x28,0xbf,0x00,0xf1,0x08,0x06,0xb8,0xf1,0x01,0x08,0xf0,0xd1,
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0x2f,0x69,0x17,0xf0,0x04,0x0f,0xfb,0xd1,0xdf,0xf8,0x1c,0x80,0x17,0xea,0x08,0x0f,
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0x03,0xd1,0x46,0x60,0x01,0x3b,0xd4,0xd1,0x03,0xe0,0x5f,0xf0,0x00,0x08,0xc0,0xf8,
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0x04,0x80,0x38,0x46,0x00,0xbe,0x00,0x00,0x00,0x00,0xee,0x07,
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@ -57,8 +57,6 @@
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#define FLASH_FW (1 << 6)
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#define FLASH_START (1 << 7)
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#define FLASH_SNB(a) ((a) << 8)
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/* FLASH_SR register bits */
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#define FLASH_BSY (1 << 0) /* Operation in progress */
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#define FLASH_QW (1 << 2) /* Operation queue in progress */
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@ -101,25 +99,31 @@
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#define FLASH_BANK1_ADDRESS 0x08100000
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#define FLASH_REG_BASE_B0 0x52002000
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#define FLASH_REG_BASE_B1 0x52002100
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#define FLASH_SIZE_ADDRESS 0x1FF1E880
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#define FLASH_BLOCK_SIZE 32
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struct stm32h7x_rev {
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uint16_t rev;
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const char *str;
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};
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/* stm32h7x_part_info permits the store each device information and specificities.
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* the default unit is byte unless the suffix '_kb' is used. */
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struct stm32h7x_part_info {
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uint16_t id;
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const char *device_str;
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const struct stm32h7x_rev *revs;
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size_t num_revs;
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unsigned int page_size;
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unsigned int page_size_kb;
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unsigned int block_size; /* flash write word size in bytes */
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uint16_t max_flash_size_kb;
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uint8_t has_dual_bank;
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uint16_t first_bank_size_kb; /* Used when has_dual_bank is true */
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uint32_t flash_regs_base; /* Flash controller registers location */
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uint32_t fsize_addr; /* Location of FSIZE register */
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uint32_t wps_group_size; /* write protection group sectors' count */
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uint32_t wps_mask;
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/* function to compute flash_cr register values */
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uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
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};
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struct stm32h7x_flash_bank {
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@ -140,18 +144,58 @@ static const struct stm32h7x_rev stm32_450_revs[] = {
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{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" }, { 0x2003, "V" },
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};
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static const struct stm32h7x_rev stm32_480_revs[] = {
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{ 0x1000, "A"},
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};
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static uint32_t stm32x_compute_flash_cr_450(uint32_t cmd, int snb)
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{
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return cmd | (snb << 8);
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}
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static uint32_t stm32x_compute_flash_cr_480(uint32_t cmd, int snb)
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{
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/* save FW and START bits, to be right shifted by 2 bits later */
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const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
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/* mask parallelism (ignored), FW and START bits */
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cmd &= ~(FLASH_PSIZE_64 | FLASH_FW | FLASH_START);
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return cmd | (tmp >> 2) | (snb << 6);
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}
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static const struct stm32h7x_part_info stm32h7x_parts[] = {
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{
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.id = 0x450,
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.revs = stm32_450_revs,
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.num_revs = ARRAY_SIZE(stm32_450_revs),
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.device_str = "STM32H74x/75x",
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.page_size = 128, /* 128 KB */
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.page_size_kb = 128,
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.block_size = 32,
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.max_flash_size_kb = 2048,
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.first_bank_size_kb = 1024,
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.has_dual_bank = 1,
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.flash_regs_base = FLASH_REG_BASE_B0,
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.fsize_addr = FLASH_SIZE_ADDRESS,
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.fsize_addr = 0x1FF1E880,
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.wps_group_size = 1,
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.wps_mask = 0xFF,
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.compute_flash_cr = stm32x_compute_flash_cr_450,
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},
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{
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.id = 0x480,
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.revs = stm32_480_revs,
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.num_revs = ARRAY_SIZE(stm32_480_revs),
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.device_str = "STM32H7Ax/7Bx",
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.page_size_kb = 8,
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.block_size = 16,
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.max_flash_size_kb = 2048,
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.first_bank_size_kb = 1024,
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.has_dual_bank = 1,
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.flash_regs_base = FLASH_REG_BASE_B0,
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.fsize_addr = 0x08FFF80C,
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.wps_group_size = 4,
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.wps_mask = 0xFFFFFFFF,
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.compute_flash_cr = stm32x_compute_flash_cr_480,
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},
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};
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@ -170,9 +214,6 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
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stm32x_info->probed = false;
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stm32x_info->user_bank_size = bank->size;
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bank->write_start_alignment = FLASH_BLOCK_SIZE;
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bank->write_end_alignment = FLASH_BLOCK_SIZE;
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return ERROR_OK;
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}
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@ -403,14 +444,15 @@ static int stm32x_protect_check(struct flash_bank *bank)
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return retval;
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}
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for (int i = 0; i < bank->num_sectors; i++) {
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bank->sectors[i].is_protected = protection & (1 << i) ? 0 : 1;
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}
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for (int i = 0; i < bank->num_prot_blocks; i++)
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bank->prot_blocks[i].is_protected = protection & (1 << i) ? 0 : 1;
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return ERROR_OK;
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}
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static int stm32x_erase(struct flash_bank *bank, int first, int last)
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{
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struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
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int retval, retval2;
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assert(first < bank->num_sectors);
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@ -436,13 +478,13 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
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for (int i = first; i <= last; i++) {
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LOG_DEBUG("erase sector %d", i);
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retval = stm32x_write_flash_reg(bank, FLASH_CR,
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FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64);
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stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
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if (retval != ERROR_OK) {
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LOG_ERROR("Error erase sector %d", i);
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goto flash_lock;
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}
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retval = stm32x_write_flash_reg(bank, FLASH_CR,
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FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64 | FLASH_START);
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stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
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if (retval != ERROR_OK) {
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LOG_ERROR("Error erase sector %d", i);
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goto flash_lock;
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@ -501,18 +543,18 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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struct target *target = bank->target;
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struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
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/*
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* If the size of the data part of the buffer is not a multiple of FLASH_BLOCK_SIZE, we get
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* If the size of the data part of the buffer is not a multiple of .block_size, we get
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* "corrupted fifo read" pointer in target_run_flash_async_algorithm()
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*/
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uint32_t data_size = 512 * FLASH_BLOCK_SIZE; /* 16384 */
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uint32_t data_size = 512 * stm32x_info->part_info->block_size;
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uint32_t buffer_size = 8 + data_size;
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struct working_area *write_algorithm;
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struct working_area *source;
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uint32_t address = bank->base + offset;
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struct reg_param reg_params[5];
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struct reg_param reg_params[6];
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struct armv7m_algorithm armv7m_info;
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struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
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int retval = ERROR_OK;
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static const uint8_t stm32x_flash_write_code[] = {
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@ -555,21 +597,23 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
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init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
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init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
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init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (word-256 bits) */
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init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash reg base */
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init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count of words (word size = .block_size (bytes) */
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init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* word size in bytes */
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init_reg_param(®_params[5], "r5", 32, PARAM_OUT); /* flash reg base */
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buf_set_u32(reg_params[0].value, 0, 32, source->address);
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buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
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buf_set_u32(reg_params[2].value, 0, 32, address);
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buf_set_u32(reg_params[3].value, 0, 32, count);
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buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->flash_regs_base);
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buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
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buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
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retval = target_run_flash_async_algorithm(target,
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buffer,
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count,
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FLASH_BLOCK_SIZE,
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stm32x_info->part_info->block_size,
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0, NULL,
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5, reg_params,
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ARRAY_SIZE(reg_params), reg_params,
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source->address, source->size,
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||||
write_algorithm->address, 0,
|
||||
&armv7m_info);
|
||||
|
|
@ -598,6 +642,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
|
|||
destroy_reg_param(®_params[2]);
|
||||
destroy_reg_param(®_params[3]);
|
||||
destroy_reg_param(®_params[4]);
|
||||
destroy_reg_param(®_params[5]);
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
|
@ -605,6 +650,7 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
uint32_t offset, uint32_t count)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
|
||||
uint32_t address = bank->base + offset;
|
||||
int retval, retval2;
|
||||
|
||||
|
|
@ -614,18 +660,18 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
}
|
||||
|
||||
/* should be enforced via bank->write_start_alignment */
|
||||
assert(!(offset % FLASH_BLOCK_SIZE));
|
||||
assert(!(offset % stm32x_info->part_info->block_size));
|
||||
|
||||
/* should be enforced via bank->write_end_alignment */
|
||||
assert(!(count % FLASH_BLOCK_SIZE));
|
||||
assert(!(count % stm32x_info->part_info->block_size));
|
||||
|
||||
retval = stm32x_unlock_reg(bank);
|
||||
if (retval != ERROR_OK)
|
||||
goto flash_lock;
|
||||
|
||||
uint32_t blocks_remaining = count / FLASH_BLOCK_SIZE;
|
||||
uint32_t blocks_remaining = count / stm32x_info->part_info->block_size;
|
||||
|
||||
/* multiple words (32-bytes) to be programmed in block */
|
||||
/* multiple words (n * .block_size) to be programmed in block */
|
||||
if (blocks_remaining) {
|
||||
retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
|
||||
if (retval != ERROR_OK) {
|
||||
|
|
@ -635,8 +681,8 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
|
||||
}
|
||||
} else {
|
||||
buffer += blocks_remaining * FLASH_BLOCK_SIZE;
|
||||
address += blocks_remaining * FLASH_BLOCK_SIZE;
|
||||
buffer += blocks_remaining * stm32x_info->part_info->block_size;
|
||||
address += blocks_remaining * stm32x_info->part_info->block_size;
|
||||
blocks_remaining = 0;
|
||||
}
|
||||
if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
|
||||
|
|
@ -653,11 +699,12 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
4. Wait for flash operations completion
|
||||
*/
|
||||
while (blocks_remaining > 0) {
|
||||
retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_PG | FLASH_PSIZE_64);
|
||||
retval = stm32x_write_flash_reg(bank, FLASH_CR,
|
||||
stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
|
||||
if (retval != ERROR_OK)
|
||||
goto flash_lock;
|
||||
|
||||
retval = target_write_buffer(target, address, FLASH_BLOCK_SIZE, buffer);
|
||||
retval = target_write_buffer(target, address, stm32x_info->part_info->block_size, buffer);
|
||||
if (retval != ERROR_OK)
|
||||
goto flash_lock;
|
||||
|
||||
|
|
@ -665,8 +712,8 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
|
|||
if (retval != ERROR_OK)
|
||||
goto flash_lock;
|
||||
|
||||
buffer += FLASH_BLOCK_SIZE;
|
||||
address += FLASH_BLOCK_SIZE;
|
||||
buffer += stm32x_info->part_info->block_size;
|
||||
address += stm32x_info->part_info->block_size;
|
||||
blocks_remaining--;
|
||||
}
|
||||
|
||||
|
|
@ -678,16 +725,6 @@ flash_lock:
|
|||
return (retval == ERROR_OK) ? retval2 : retval;
|
||||
}
|
||||
|
||||
static void setup_sector(struct flash_bank *bank, int start, int num, int size)
|
||||
{
|
||||
for (int i = start; i < (start + num) ; i++) {
|
||||
assert(i < bank->num_sectors);
|
||||
bank->sectors[i].offset = bank->size;
|
||||
bank->sectors[i].size = size;
|
||||
bank->size += bank->sectors[i].size;
|
||||
}
|
||||
}
|
||||
|
||||
static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
|
||||
{
|
||||
/* read stm32 device id register */
|
||||
|
|
@ -779,35 +816,45 @@ static int stm32x_probe(struct flash_bank *bank)
|
|||
/* did we assign flash size? */
|
||||
assert(flash_size_in_kb != 0xffff);
|
||||
|
||||
/* calculate numbers of pages */
|
||||
int num_pages = flash_size_in_kb / stm32x_info->part_info->page_size;
|
||||
|
||||
/* check that calculation result makes sense */
|
||||
assert(num_pages > 0);
|
||||
|
||||
if (bank->sectors) {
|
||||
free(bank->sectors);
|
||||
bank->sectors = NULL;
|
||||
}
|
||||
|
||||
bank->base = base_address;
|
||||
bank->num_sectors = num_pages;
|
||||
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
|
||||
bank->size = flash_size_in_kb * 1024;
|
||||
bank->write_start_alignment = stm32x_info->part_info->block_size;
|
||||
bank->write_end_alignment = stm32x_info->part_info->block_size;
|
||||
|
||||
/* setup sectors */
|
||||
bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
|
||||
assert(bank->num_sectors > 0);
|
||||
|
||||
if (bank->sectors)
|
||||
free(bank->sectors);
|
||||
|
||||
bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
|
||||
bank->num_sectors);
|
||||
|
||||
if (bank->sectors == NULL) {
|
||||
LOG_ERROR("failed to allocate bank sectors");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
bank->size = 0;
|
||||
|
||||
/* fixed memory */
|
||||
setup_sector(bank, 0, num_pages, stm32x_info->part_info->page_size * 1024);
|
||||
/* setup protection blocks */
|
||||
const uint32_t wpsn = stm32x_info->part_info->wps_group_size;
|
||||
assert(bank->num_sectors % wpsn == 0);
|
||||
|
||||
for (int i = 0; i < num_pages; i++) {
|
||||
bank->sectors[i].is_erased = -1;
|
||||
bank->sectors[i].is_protected = 0;
|
||||
bank->num_prot_blocks = bank->num_sectors / wpsn;
|
||||
assert(bank->num_prot_blocks > 0);
|
||||
|
||||
if (bank->prot_blocks)
|
||||
free(bank->prot_blocks);
|
||||
|
||||
bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
|
||||
bank->num_prot_blocks);
|
||||
|
||||
if (bank->prot_blocks == NULL) {
|
||||
LOG_ERROR("failed to allocate bank prot_block");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
stm32x_info->probed = true;
|
||||
stm32x_info->probed = 1;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -946,6 +993,7 @@ static int stm32x_mass_erase(struct flash_bank *bank)
|
|||
{
|
||||
int retval, retval2;
|
||||
struct target *target = bank->target;
|
||||
struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
|
|
@ -957,11 +1005,13 @@ static int stm32x_mass_erase(struct flash_bank *bank)
|
|||
goto flash_lock;
|
||||
|
||||
/* mass erase flash memory bank */
|
||||
retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64);
|
||||
retval = stm32x_write_flash_reg(bank, FLASH_CR,
|
||||
stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
|
||||
if (retval != ERROR_OK)
|
||||
goto flash_lock;
|
||||
|
||||
retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64 | FLASH_START);
|
||||
retval = stm32x_write_flash_reg(bank, FLASH_CR,
|
||||
stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
|
||||
if (retval != ERROR_OK)
|
||||
goto flash_lock;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue