Clang static analyzer says that in certain cases "Assigned value is
garbage or undefined" there.
Change-Id: Ib35a4cf7a553ba9461270a0dc4c4b9b205091e73
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4338
Tested-by: jenkins
Tested on FRDM-K28F. Thanks to Thomas Varghese for donating the kit.
Change-Id: Idcdd8bcf992acebd19e5335f7f833356500c45dd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4255
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The Flash Configuration Field on Kinetis devices requires protection
because it is located in program flash space (at 0x400) and writing
an improper data to it may permanently lock the device. Even an erased
flash sector containing FCF engages security lock (not permanent one)
on the next reset or power cycle.
'kinetis fcf_source protection' mode was introduced in the change #3562.
Flash driver in this mode sets FCF immediately after sector erase to
prevent unintentional security lock. To do so the driver needs to know
FCF values before flash image data is actually processed. Flash
protection bits are available in bank structure, FOPT can be set by
'kinetis fopt' command and securing device by FSEC is not supported.
Nevertheless an inexperienced user flashed the device using an image
with FCF values different from those set in OpenOCD config and
concluded programming did not work as some verify errors showed.
This change tries to write maximum possible from image data
retaining FCF protection.
Check FCF in programmed data and report if some field differs from
values set by OpenOCD flash block protection and 'kinetis fopt' command.
Warn user about verify errors caused by FCF protection.
On devices with ECC flash (K26, K66 and KV5x) it is impossible to change
already programmed FCF - it would result in an ECC error. As FCF was
written just after erase in 'kinetis fcf_source protection' mode
the warning issued during flash write is the only possible action.
On non-ECC flash devices use cumulative flash programming to
set FCF values requested in programmed image data.
Use FSEC from programmed data only if it does not request a secure
mode. Device can be secured only in 'kinetis fcf_source write' mode.
Use FOPT from programmed data if its value was not configured
in OpenOCD config by 'kinetis fopt' command.
Change-Id: If65fbbd7700069f57e4ae32234dce371bff93674
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4228
Tested-by: jenkins
Reviewed-by: Robert Foss <robert.foss@memcpy.io>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reading options word can fail, so this needs to be handled.
Reported by Clang static analyzer.
Change-Id: I9754cab9c4446fa2b20d4b44b0e20724d1bc1beb
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4352
Tested-by: jenkins
Reviewed-by: Tim "mithro" Ansell <mithro@mithis.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit contains a rewrite of the jtagspi protocol and covers both
changes in the jtagspi.c openocd driver and the bscan_spi
(xilinx_bscan_spi) proxy bitstreams. The changes are as follows:
1. Always perform IR scan to ensure proper clearing of BYPASSed DRs.
2. Insert alignment cycles for all BYPASSed TAPs:
The previous logic was erroneous. The delay in clock cyles from a bit
written to the jtag interface to a bit read by the jtag interface is:
* The number of BYPASSed TAPs before this (jtagspi) tap
* The length of the jtagspi data register (1)
* The number of BYPASSed TAPs before this one.
I.e. it is just the number of enabled TAPs. This also gets rid of the
configuration parameter DR_LENGTH.
3. Use marker bit to start spi transfer
If there are TAPs ahead of this one on the JTAG chain, and we are in
DR-SHIFT, there will be old bits toggled through first before the first
valid bit destined for the flash.
This delays the begin of the JTAGSPI transaction until the first high bit.
4. New jtagspi protocol
A JTAGSPI transfer now consists of:
* an arbitrary number of 0 bits (from BYPASS registers in front of the
JTAG2SPI DR)
* a marker bit (1) indicating the start of the JTAG2SPI transaction
* 32 bits (big endian) describing the length of the SPI transaction
* a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
* an arbitrary number of cycles (to shift MISO/TDO data through
subsequent BYPASS registers)
5. xilinx_bscan_spi: clean up, add ultrascale
This is tested on the following configurations:
* KC705: XC7K325T
* Sayma AMC: XCKU040
* Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG
adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx
Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma
* Custom board with Lattice FPGA + XC7A35T
* CUstom board with 3x XCKU115-2FLVA1517E
Change-Id: I7361e9fb284ebb916302941735eebef3612aa103
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4236
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This should allow to process any path names excluding those that have
curly braces.
Change-Id: I87bf9ddede11e2b28d5826878eb1338143f73c03
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4083
Tested-by: jenkins
Theese devices do not have a gap in sector numbering.
The driver translates sectors numbers 12 13... to 16 17... as used on dual
bank flash devices. Therefore erase of sector 12 and above fails with error
'stm32x device protected'
on F413/423.
Drop sector number translation for devices without has_large_mem flag.
Change-Id: I65531c0dfe02e2fd0f3d68f0615e0926e9901391
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4299
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
A protection block comprises two adjacent sectors in dual bank mode.
As there are 64 and 128kB sectors joined in blocks 2 and 8, block size
should be computed as a sum of sector sizes.
Change-Id: Ie915df8cf7ca232c4565d7e0c514c8933e71fdfe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4271
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
GCC7 with -Wall warns about possible string truncation with
snprint()-type functions with "directive output may be truncated writing
1 byte into a region of size between 0 and 9
[-Werror=format-truncation=]" + "note: ‘snprintf’ output between 5 and
14 bytes into a destination of size 12" (or similar). Fix this by
increasing sizes of buffers.
See https://gcc.gnu.org/gcc-7/changes.html
Change-Id: Ib848f2a56dd658783534158947ae1be7c0e99d45
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/4175
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
GCC7 with -Wextra warns about switch-case blocks which fallthrough with
"this statement may fall through [-Werror=implicit-fallthrough=]". This
can be fixed by adding "special" comments: "/* fallthrough */".
See https://gcc.gnu.org/gcc-7/changes.html
Change-Id: Iba0be791dbdd86984489b2d9a0592bb59828da1e
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/4174
Tested-by: jenkins
Renaming of all nrf51 NOR flash code to nrf5, as to prepare the
code for being able to flash nrf51 and nrf52 chips.
The nrf51 command is retained for backwards compatability.
"nRF5" is also the name Nordic Semiconductor uses to describe
both the nrf51 and nrf52 chips.
Change-Id: I5f4e3f1ec780184b28ad44f735a746e68908c502
Signed-off-by: Slowcoder <slowcoder@gmail.com>
Reviewed-on: http://openocd.zylin.com/4209
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This cleans up the list of supported nrf51 chips considerably.
Change-Id: Ic74685657bb72a8703c0a49df4c48c54604ec2a7
Signed-off-by: Slowcoder <slowcoder@gmail.com>
Reviewed-on: http://openocd.zylin.com/4208
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Trying to read the L0 idcode at the L1 idcode address 0xE0042000 often
resulted in an uncatched error. Reading at the right L0 address 0x40015800
afterwards results in reading 0. So access to the device is denied..
Change-Id: I6de92cf99a5d5d46c72f9ba055613cbc5753a951
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3883
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch adds support for Blue Gecko and Mighty Gecko chips from
Silabs.
They have different EFM32_MSC_REGBASE and LOCK register offset.
Based on the original patch from Andreas Kemnade.
Change-Id: I166c14960ced7c880b68083badd1b31372fefabe
Cc: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-on: http://openocd.zylin.com/4034
Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com>
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: chrysn <chrysn@fsfe.org>
Use unsigned constant for left shift operation in order to avoid the
following error with GCC >= 6.0:
../src/flash/nor/stm32f2x.c: In function ‘stm32x_handle_unlock_command’:
../src/flash/nor/stm32f2x.c:1324:67: error: left shift of negative value [-Werror=shift-negative-value]
stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1 << bank->num_sectors);
Change-Id: I0ac082bd0dbb8dc2f61ffff8fdf486ab7962d2e0
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4207
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Anton Fosselius <anton.fosselius@gmail.com>
Reviewed-by: Esben Haabendal <esbenhaabendal@gmail.com>
IDs for STM32F722, F723, F413 and F423 added, handling of PCROP
for F722/723 and additional nWPRT bits for F413/423 implemented.
The additional protection bit positions for F413/423 conflict
with other options bits for the F7xx variants, additionally the
last two sectors share a common bit.
Protection for F413 and F767/777 now use protection blocks
rather sectors for dealing with protections bits.
Checking for halted state in 'lock' and 'unlock' removed: When
PCROP is activated in F723, halted state is not detected properly,
but lock/unlock sequence is required to disable PCROP.
Tested with STM32F723E-Disco, STM32F413ZH-Nucleo.
Change-Id: Ie6ddab47a9ae8461087d369b4f289b7f9d1e031c
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4045
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
A footnote in RM0038r14.
Change-Id: Ic31894d846fbbe917a7290b2b7ff8fb582bb65da
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4198
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If a MCU has FlexNVM partitioned as EEPROM backup only
(no data flash), kinetis_probe_chip() detects zero fcfg2_maxaddr1
and adjusts flash banks count to 1, what is obviously wrong.
The change limits the test to devices without FlexNVM.
Computation of program flash/FlexNVM blocks is now more robust.
Missing case 0x07 is added to switch (fcfg1_depart)
Change-Id: I0bd6030a0fe1ab62aeb0223bbdf2aee1505bf6a0
Reported-by: simon.haines@scalardata.com
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4180
Tested-by: jenkins
Reviewed-by: Simon Haines <simon.haines@scalardata.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I2692b9877a7f877104528f279a69e8cc1cfbcdbf
Reported-by: David Miller Lowe <milhead@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4173
Tested-by: jenkins
Reviewed-by: Miller Lowe <miller.lowe@trailtech.net>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Recognise the family number for Silicon Labs EZR32HG devices and
select the correct flash page size.
Change-Id: I876e930f3a9f679557fa0d0acac33e9bbfb28c46
Signed-off-by: Richard Watts <rrw@kynesim.co.uk>
Reviewed-on: http://openocd.zylin.com/3934
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Make 'offset' and 'length' parameters optional, if both are omitted
simply read the whole flash bank.
Additionally, check if the 'offset' and 'length' arguments are out of
bounds of the flash bank.
Change-Id: Ib9c1b0538a2c78ebcf702e2da11468dff407f8ff
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3862
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Respect the flash bank boundary and write only to the remaining part of
the bank even if the file content is larger.
Change-Id: I8f4c1b161c103a77bdb30c6bf052293b5ed48c41
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3861
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Make the 'offset' parameter optional, if omitted simply start at the
beginning of the flash bank.
Additionally, check if the argument is out of bounds of the flash bank.
Change-Id: I8e9632b539ad9e83211e1ac6a06da4c8109cbc60
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3860
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Respect the flash bank boundary and compare only the remaining content
of the bank even if the file content is larger.
Change-Id: I4d75979c7893fdd4d18372fa6b0321a0486b4fa9
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3859
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add support for flashing newer members of the NXP Kinetis KW family
Supported devices:
- KW20Z
- KW30Z
- KW40Z
- KW21Z
- KW31Z
- KW41Z
The earlier KW2xD and KW01Z devices are already supported by the code
for the older K-series.
Verified working on the FRDM-KW41Z development board.
Tested flashing both via GDB `load` and directly via OpenOCD flash
write commands.
Change-Id: I73eae477127a8b54a33005b3b526b5439450a808
Signed-off-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-on: http://openocd.zylin.com/4104
Tested-by: jenkins
Reviewed-by: Johann Fischer <johann_fischer@posteo.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This device differs a lot from others in KL series.
Unfortunately the System Integration Module, where device
identification resides, moved to a new address so probe now have
to try both addresses of SIM_SDID.
Introduce a new bank creation option: -sim-base to ensure error free probe.
WDOG32 is slightly different from KE1x and on different address.
System Mode Controler changed layout to word aligned.
Change-Id: I2c9dca0c4ad4228fcc941d6078d15f5e394833ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4059
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Active watchdog forces reset during armv7m_checksum_memory()
in verify_image command if run just after reset init.
COP watchdog in KL series and WDOG32 in KE1 series
have longer timeout however they need to be disabled too.
The change extends 'kinetis disable_wdog' command to optionally
probe the chip and use appropriate algorithm to disable watchdog.
Setting of cache type is also split from flash_support flags.
Tcl command 'kinetis disable_wdog' is called in reset-init event.
Change-Id: I3191e230f38b679ed74f2a97fe323ef8fb3fe22e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3901
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Kinetis flash driver services huge number of MCU types. They have
one, two or four flash banks with option of FlexNVM. It would
require ~36 config files just for Kx series, more for KLx, KVx and KE1x.
The change implements alternative approach:
- configuration file creates just one pflash bank (common for all devices)
- when a device is probed, additional pflash or flexnvm banks are created
based on flash layout of the connected MCU
- created banks have names with optional numbering e.g. kx.pflash0 kx.pflash1
kx.flexnvm0 kx.flexnvm1
- the first bank gets renamed if numbering is used
Automatic bank creation is enabled by tcl command 'kinetis create_banks'.
Used solution has a drawback: other banks than pflash0 are not accessible
until pflash0 is probed. Fortunately gdb attach and standard programming
accesses banks in right sequence.
Change-Id: I5b9037cbefdb8a4176b7715fbcc3af4da4c1ab60
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3925
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Kinetis flash driver probed and decoded chip repeatedly for each flash
bank. Bank ordering used global bank number so multi-target
configuration was broken.
The change introduces kinetis_probe_chip() which reads SIM SDID
and SIM FCFG registers, decodes Kinetis series and family
and fills struct kinetis_chip. This probe runs once for all banks.
struct kinetis_chip contains pointers to all flash banks embeded
in the MCU. It simplifies iteration over all or specific MCU banks.
kinetis_probe_chip() generates MCU name and some informational messages
are improved.
Change-Id: I990db5c63ba490667eec0e5459086d83936662fb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3924
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Real time control MCU has a Cortex-M7 and numerous changes in flash layout.
Introduced a new ID of MDM-AP.
While on it a LOG_DEBUG format error fixed.
Change-Id: I1018660ce0c3dd63ac5e2563408fabff3c3daef7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3900
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Secure devices KL81Z7 and KL82Z7 have no SERIESID field in ID register
so they have to be decoded in Kx branch (not KLx).
The flash controller in KL8x and also in K8x devices does not implement
FTFx_CMD_BLOCKSTAT command. Fix kinetis_blank_check() to work properly
using FTFx_CMD_SECTSTAT command only.
Introduce a new flag FS_NO_CMD_BLOCKSTAT to avoid use of FTFx_CMD_BLOCKSTAT
on these devices.
Change-Id: I3ff58718480acd8cce69f618f71667b6b1d9c4f3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3898
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The new Kinetis KE1x families use FTFE flash controller unlike KE0x.
Also SDID coding corresponds to new K, KL and KV families.
That's why KE1x is handled by kinetis driver instead of kinetis_ke
Change-Id: Ibb73e28e41dfbb086e761e1f006b089825dab854
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3896
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tim Newsome
Paul Fertser
Daniel Kucera
Tomas Vanek
Megan Wachs
Robert Jordens
barthess
Alexandre Torgue
Freddie Chopin
Slowcoder
Uwe Bonnes
Andrea Merello
Marc Schink
Liviu Ionescu
Andreas Bolsch
Karl Palsson
Richard Watts
Joakim Nohlgård