Commit Graph

8215 Commits

Author SHA1 Message Date
Paul Fertser fa86553e76 x86_32_common: fix some warnings
Mostly "Dead assignment" reported by Clang static analyzer.

Change-Id: Ibf81d2ba2462570ee3a40e57a60c55a1d1fa0c00
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4351
Tested-by: jenkins
2018-01-30 07:34:32 +00:00
Tim Newsome 0f0c5b1ff5 Merge branch 'riscv' into sysbusbits
Change-Id: Ib7921c73a4bdd586703031be3509d1dec9bb3913
2018-01-29 11:39:14 -08:00
Tim Newsome ec543bdc7b
Merge pull request #198 from riscv/hartsellen
Detect hartsellen, limiting which harts we probe
2018-01-29 11:11:00 -08:00
Tomas Vanek dd890d4cad arm_adi_v5: fix return value of mem_ap_read/write for size 0
Unhandled marginal case produced a warning in Clang static analyzer.

Change-Id: I3e2fc4182fa4f863acfb972b1e7a512fce5bf33a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/4357
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-29 14:47:40 +00:00
Matthias Welwarsky 1ac0f5d493 aarch64: clean up scan-build errors
scan-build reported a couple of problems with code in aarch64.c,
this patch cleans them up. No functional changes.

Change-Id: Ie210237ddc840a8bbcd535f86a3a5faf473132f2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4346
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-29 08:24:17 +00:00
Paul Fertser e60573c528 jtag: drivers: usb_blaster: clarify lowlevel driver selection code
This patch should make the code logic more transparent and user
notifications more useful.

It also fixes a warning "array subscript is below array bounds" that
leads to FTBFS on Raspbian GNU/Linux 8 (jessie).

Change-Id: I626b6a5bc013dfee7d36cf196f0abab981d30675
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3931
Tested-by: jenkins
2018-01-27 17:16:02 +00:00
Tim Newsome 6a98fb7076 Detect hartsellen, limiting which harts we probe
Tested with doctored spike with hartsellens of 0, 1, 3, and 10.

Change-Id: I97f57c7d03b076792d5ecd66545d9b9e853ed515
2018-01-26 16:39:58 -08:00
Tim Newsome 5184c32125 Clear errors that we see.
Also WIP towards handling busy errors, but I'm putting that on hold
while I change the spec...

Change-Id: Iccf47048da46e75b0d769e56004fd783bba1dbf0
2018-01-26 15:43:05 -08:00
Tim Newsome b67379700b Add support for v1 system bus access.
This is functional, but doesn't handle errors.

Change-Id: Ifb46af1b0b567f3c2a6135b2ad5eb7ba63a3f595
2018-01-26 15:43:05 -08:00
Tim Newsome beac00149c Use new debug_defines.h
Change-Id: Iefc8424343dbed05fa9dacc626829955fc16f299
2018-01-26 15:41:45 -08:00
Daniel Kucera a0c4c9e717 nor/nrf5: added nrf51822 QFAAH2
Change-Id: I59725e098371c63ec3e6aa1d91bfed36b824a182
Signed-off-by: Daniel Kucera <daniel.kucera@gmail.com>
Reviewed-on: http://openocd.zylin.com/4334
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-26 22:38:27 +00:00
Matthias Welwarsky a640f139ba aarch64: implement mmu on/off for aarch32
add decoding of aarch32 core modes (register layout is compatible)

Change-Id: I34c3146a7b1f836d3006be2b76b036da055b3d3e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4374
Tested-by: jenkins
Reviewed-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-26 10:53:09 +00:00
Tim Newsome 68c57474f9
Merge pull request #192 from riscv/memlog
Make all memory logging lines consistent.
2018-01-25 10:51:35 -08:00
Tim Newsome 64f1f7b1c1 Add read buffer to bitbang, improving performance.
Previously for every bit scanned OpenOCD would write the bit, wait for
that bit to be scanned, and then read the result. This involves at least
2 context switches. Most of the time the next bit scanned does not
depend on the last bit we read, so with a buffer we now write a bunch of
bits to be scanned all at once, and then we wait for them all to be
scanned and have a result.

This reduces the time for one testcase where OpenOCD connects to a
simulator from 12.30s to 5.35s!

Running all our tests went from 13m13s to 3m55s.

Change-Id: Ie9fcea043ac1d7877a521125334ed47d4b3e1615
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4312
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2018-01-25 16:44:06 +00:00
Christopher Head 2428722a23 Use timeval helpers
Some of these changes actually fix broken comparisons which could
occasionally fail. Others just clean up the code and make it more clear.

Change-Id: I6c398bdc45fa0d2716f48a74822457d1351f81a5
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4380
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-25 16:43:49 +00:00
Christopher Head e0fc7a54f2 Add timeval_compare helper function
Change-Id: Id75727a150912ff778a4fa32ad56467da33a6324
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4379
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-25 16:43:45 +00:00
Paul Fertser e22c6484ea tcl: target: klx: use 1KiB for working area
Some parts have only that much. Reported by robertfoos_ on IRC.

Change-Id: I684fdccfa62cf726466ddc467543a990fd88c4dc
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4369
Reviewed-by: Robert Foss <robert.foss@memcpy.io>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-25 16:41:32 +00:00
Tomas Vanek b7be0a873c flash Kinetis: add K27 and K28 devices
Tested on FRDM-K28F. Thanks to Thomas Varghese for donating the kit.

Change-Id: Idcdd8bcf992acebd19e5335f7f833356500c45dd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4255
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2018-01-25 16:40:58 +00:00
Tomas Vanek e3f3b77729 flash Kinetis: make FCF protection more user friendly
The Flash Configuration Field on Kinetis devices requires protection
because it is located in program flash space (at 0x400) and writing
an improper data to it may permanently lock the device. Even an erased
flash sector containing FCF engages security lock (not permanent one)
on the next reset or power cycle.

'kinetis fcf_source protection' mode was introduced in the change #3562.
Flash driver in this mode sets FCF immediately after sector erase to
prevent unintentional security lock. To do so the driver needs to know
FCF values before flash image data is actually processed. Flash
protection bits are available in bank structure, FOPT can be set by
'kinetis fopt' command and securing device by FSEC is not supported.

Nevertheless an inexperienced user flashed the device using an image
with FCF values different from those set in OpenOCD config and
concluded programming did not work as some verify errors showed.

This change tries to write maximum possible from image data
retaining FCF protection.

Check FCF in programmed data and report if some field differs from
values set by OpenOCD flash block protection and 'kinetis fopt' command.
Warn user about verify errors caused by FCF protection.

On devices with ECC flash (K26, K66 and KV5x) it is impossible to change
already programmed FCF - it would result in an ECC error. As FCF was
written just after erase in 'kinetis fcf_source protection' mode
the warning issued during flash write is the only possible action.

On non-ECC flash devices use cumulative flash programming to
set FCF values requested in programmed image data.
Use FSEC from programmed data only if it does not request a secure
mode. Device can be secured only in 'kinetis fcf_source write' mode.
Use FOPT from programmed data if its value was not configured
in OpenOCD config by 'kinetis fopt' command.

Change-Id: If65fbbd7700069f57e4ae32234dce371bff93674
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4228
Tested-by: jenkins
Reviewed-by: Robert Foss <robert.foss@memcpy.io>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-25 16:40:31 +00:00
Paul Fertser e3a5f1613b flash: nor: stm32l4x: fix warning in probe
Reading options word can fail, so this needs to be handled.

Reported by Clang static analyzer.

Change-Id: I9754cab9c4446fa2b20d4b44b0e20724d1bc1beb
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4352
Tested-by: jenkins
Reviewed-by: Tim "mithro" Ansell <mithro@mithis.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-25 07:22:57 +00:00
Paul Fertser f02327d859 server: add safeguards against printing bogus port number
Clang static checker emits "Assigned value is garbage or undefined"
warning there as it can't prove that when the socket descriptor is
AF_INET/SOCK_STREAM and getsockname doesn't return an error, sin_port
is guaranteed to be filled in.

Pacify it by obvious means.

Change-Id: I43b5e5ceb41c07d523a81b34a25490c4c5f49a70
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4350
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-25 07:22:16 +00:00
Tomas Vanek ff623b83fc target, arm_adi_v5: catch two allocation errors
Command
	mdw 0 0x40000000
triggers Segmentation fault on an arm.
Size parameter is a nonsence that may happen e.g. if you
mistype mdw instead of mww.

Add checking for calloc() NULL return in mdb/h/w.

Use calloc() instead of malloc() as multiplication
count * sizeof(uint32_t) overflows for size >= 0x40000000.

Change-Id: I968c944d863d1173ef932a7077d526fccb9381ae
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4349
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-25 07:20:48 +00:00
Tim Newsome 2d263bae84 Make all memory logging lines consistent.
Also reduce a few 64-bit variables to 32 bits, which is all they need.

Change-Id: I23e431b7eed4a63803add93a1bb328a3631631d6
2018-01-24 13:53:11 -08:00
Tim Newsome 42e601afc1
Merge pull request #191 from riscv/scanbuild
Fix some niggles found by clang's static analysis.
2018-01-24 07:59:47 -08:00
Tim Newsome 553a63808c Fix some niggles found by clang's static analysis.
Change-Id: Id476227e1bd02e067f0cc4da9bc7ffb3d9d30535
2018-01-23 15:16:23 -08:00
Megan Wachs 5e22040b67
SPI Flash: add 256Mb SPI Part by ISSI 2018-01-20 13:34:53 -08:00
Tim Newsome 5ea8bb90df
Merge pull request #189 from riscv/examine_err
Add some error checking to examine().
2018-01-19 17:06:34 -08:00
Tim Newsome 446044db89
Merge pull request #187 from riscv/fespi
Make compilation command specify architecture.
2018-01-19 16:28:02 -08:00
Tim Newsome 3839cbf0ad Add some error checking to examine().
Fixes #183.

Change-Id: I6fb45adf4c97ea339c9d4ca3b372a09b18e3b56e
2018-01-19 13:58:02 -08:00
Tim Newsome 1ab7e910fd Make compilation command specify architecture.
Fixes issue #180.

Change-Id: Icf180ae87db92840930044f1aa3129466cf43fad
2018-01-19 11:41:17 -08:00
Tim Newsome cb543e804d
Merge pull request #184 from riscv/cleanup
Remove dead code.
2018-01-17 15:08:30 -08:00
Marc Schink edb6796286 Fix Jim interpreter memory leak
Change-Id: I71d7d97e7dc315c42fc43b65cb5fcecd7bdfb581
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2959
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-17 07:52:35 +00:00
Oleksij Rempel 2bd78e1239 target: add initial imx7.cfg
Change-Id: I899a215049ff0bc8840463c71018867ef71b5b90
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4190
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
2018-01-16 09:15:36 +00:00
Matthias Welwarsky 685cdf86ea aarch64: speed up first examination
Don't use atomic dap operations when not necessary. Also remove
loop trying to set core power request, didn't find a platform
where it actually worked and it's slowing examination down.

Change-Id: I44e5c2f289f951b8f4579f08a841172404a52053
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4143
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-16 09:06:02 +00:00
Matthias Welwarsky 1482c26a4e aarch64: simplify mode and state handling
Aarch32 and Aarch64 modes don't conflict in CPSR, no need to deconflict
ARMv7-M profile modes either.


Change-Id: I4c437dfa657f9e8a1da3687bc9f21435384b7881
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4144
Tested-by: jenkins
Reviewed-by: Yao Qi <qiyaoltc@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-16 09:05:49 +00:00
Matthias Welwarsky b3d29cb544 aarch64: add 'maskisr' command
Allow to configure ISR masking during single-step and add
handling for stepping over WFI with ISR masked.

Change-Id: I7918be7bcda6a1d9badac44fc36c59b52f662fef
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4023
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-16 09:05:41 +00:00
Tim Newsome 7f368468c8 Remove dead code.
Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
2018-01-15 12:07:20 -08:00
Jiri Kastner f7836bbc75 arm_adi_v5: added some partnumbers found in tegra 186 and tegra 210
Change-Id: Icd4137f3e266364d9728672bd2359fbd9a6c8ce9
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/4160
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-14 13:31:50 +00:00
Robert Jordens 867bdb2e92 jtagspi: new protocol that includes transfer length
This commit contains a rewrite of the jtagspi protocol and covers both
changes in the jtagspi.c openocd driver and the bscan_spi
(xilinx_bscan_spi) proxy bitstreams. The changes are as follows:

1. Always perform IR scan to ensure proper clearing of BYPASSed DRs.
2. Insert alignment cycles for all BYPASSed TAPs:

  The previous logic was erroneous. The delay in clock cyles from a bit
  written to the jtag interface to a bit read by the jtag interface is:

  * The number of BYPASSed TAPs before this (jtagspi) tap
  * The length of the jtagspi data register (1)
  * The number of BYPASSed TAPs before this one.

  I.e. it is just the number of enabled TAPs. This also gets rid of the
  configuration parameter DR_LENGTH.

3. Use marker bit to start spi transfer

  If there are TAPs ahead of this one on the JTAG chain, and we are in
  DR-SHIFT, there will be old bits toggled through first before the first
  valid bit destined for the flash.
  This delays the begin of the JTAGSPI transaction until the first high bit.

4. New jtagspi protocol

  A JTAGSPI transfer now consists of:

  * an arbitrary number of 0 bits (from BYPASS registers in front of the
    JTAG2SPI DR)
  * a marker bit (1) indicating the start of the JTAG2SPI transaction
  * 32 bits (big endian) describing the length of the SPI transaction
  * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
  * an arbitrary number of cycles (to shift MISO/TDO data through
    subsequent BYPASS registers)

5. xilinx_bscan_spi: clean up, add ultrascale

This is tested on the following configurations:

* KC705: XC7K325T
* Sayma AMC: XCKU040
* Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG
  adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx
  Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma
* Custom board with Lattice FPGA + XC7A35T
* CUstom board with 3x XCKU115-2FLVA1517E

Change-Id: I7361e9fb284ebb916302941735eebef3612aa103
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4236
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 19:36:42 +00:00
Marc Schink 22ad1c0f60 server/telnet: Use proper data types
Change-Id: Ie7588e311fa5155d5ee73148dee3d0d931bfc7f5
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3413
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 15:33:52 +00:00
Patrick Stewart 1003bc7be7 ftdi swd: disable SWD output pin during input
* Disables the data output pin while SWD is reading, so that a simple FTDI
   SWD interface can be made by connecting TCK to SWD_CLK and TDI+TDO directly
   to SWDIO. Enabled by setting SWDIO_OE to 0.

Change-Id: I7d3b71cf3f4eea163cb320aff69ed95d219190bd
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Signed-off-by: Roger Lendenmann <roger.lendenmann@intel.com>
Reviewed-on: http://openocd.zylin.com/2274
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
2018-01-13 11:37:13 +00:00
Paul Fertser ab25205bbf checkpatch: fix more "unescaped left brace" warnings
Unescaped left brace in string literals is deprecated since perl
v5.21.1.

Not a Perl programmer here so please review!

Change-Id: I724d8fa616d603e032e07afb9b8933e0ec95045b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3801
Tested-by: jenkins
2018-01-13 09:56:05 +00:00
Tim Newsome 2f6f607507 Accept 64-bit addresses in CRC requests.
Change-Id: I6a3e97ae8ffb4dc2ca1197a8102cb9ba34de0a1e
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4317
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-01-13 09:52:13 +00:00
Tim Newsome 79cbeafe9f Support listening on port 0.
When listening on port 0, the system will assign a random open port. We
use this to run multiple OpenOCD instances against multiple simulators
as part of regression testing. This mechanism means the various test
instances don't have to coordinate to ensure they don't reuse any ports.

The required changes are minimal:
1. Don't increment the port number when it's 0.
2. Print out which port was assigned by the system.

Change-Id: I404c801fc405e9d8eb8420562c02e78d4db6242f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4316
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-01-13 09:51:42 +00:00
Jiri Kastner e9493cc20a ejtag: added missing instructions.
added missing instructions from latest available ejtag specification
(MD00047 v6.1 at time of writting) for trace control, fast data channel
and pcsample.

Change-Id: I30293951611265ffc2bd896f9d3ca6b310e5cac6
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/3950
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:46:00 +00:00
Marc Schink e0010c3e6f server/telnet: Handle Ctrl+A and Ctrl+E
Handle the Ctrl+A and Ctrl+E shortcuts which move the cursor to the
beginning and end of the command line, respectively.

Change-Id: I89fa5fd3c5edeb08a3f9320fda766f72ce9d7f64
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3415
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:41:26 +00:00
Karl Palsson 9cd74c113c profiling: write "correct" sample rate to gmon output
This duration vs sample count is _significantly_ closer to the truth
than simply declaring the value to be 100Hz.

Change-Id: Ie8d8bdf1959e1aa7cead0631cd2c86afe77d1efc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4221
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:32:43 +00:00
Karl Palsson 4e0371bf71 hla_target: allow non-intrusive profiling on cortex-m
Leverages the existing work that added profiling via DWT_PCSR.

hla_target doesn't have direct access to the mem_ap for doing a bulk
repeated read, but simply reading the DWT_PCSR register repeatedly is
still ~2 order of magnitude faster than halt/resume.

Change-Id: Ibe451aa95143694398370fdad6939cfb6191d56f
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4220
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:31:36 +00:00
Simon Schubert 64b0d5aac0 cortex_m: add profiling function
Use DWT_PCSR if present (reads nonzero); otherwise do halt-and-sample pc.

Signed-off-by: Simon Schubert <2@0x2c.org>
Change-Id: Id2dc4665e5008cc497a2e6e6493522d038d5af42
Reviewed-on: http://openocd.zylin.com/4211
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:29:59 +00:00
Felipe Balbi 2b44b52478 target: lakemon: implement assert_reset and deassert_reset
We're using an I/O port reset by default. The only board currently
supported (Galileo) doesn't have SRST routed on the JTAG connector.

When using 'reset halt', we must rely on Reset Break because our
adapters don't have support for PREQ#/PRDY# signals.

Tested with Intel Galileo GEN2.

Change-Id: Ia406e31c156f8001717d5b6a08bd03f71de790d3
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4016
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:25:34 +00:00