c61b3efe9a
riscv: Retry failed memory reads
2017-03-22 17:51:46 -07:00
98420e377a
riscv: add missing variable declaration.
2017-03-21 23:47:21 -07:00
09da0c812f
Clear autoexec correctly
2017-03-21 17:20:11 -07:00
6033850415
Wrong autoexec
2017-03-21 17:20:11 -07:00
0c790d385d
Builds
2017-03-21 17:20:11 -07:00
c09ccbcc7c
Merge pull request #20 from sifive/delay_after_autoexec
...
riscv-v13: wait for idle in read_memory
2017-03-21 13:18:26 -07:00
a70e628620
riscv-v13: wait for idle in read_memory
...
read_memory was doing autoexec-initialized commands, but wasn't using
ac_busy_delay to add delay or wait between the commands. This isn't the optimal
solution, but the whole read_memory sequence needs to be made more efficient
anyway, so this was the quick and dirty solution.
2017-03-15 17:23:21 -07:00
bb39d3b17e
Remove more cruft.
...
Change-Id: I24d545cc259927301851fad446f812e95fd1c557
2017-02-27 20:27:07 -08:00
8785b256cb
Merge pull request #18 from sifive/halt_correctly
...
riscv: Ensure that hart is halted before attempting to examine it.
2017-02-27 20:17:42 -08:00
7f13e90505
riscv: Ensure that hart is halted before attempting to examine it.
2017-02-27 18:53:50 -08:00
b4d38d0997
Remove cruft.
...
Change-Id: I3a370aa3a478ab84c9b2afff7b3f581bd7dc5e06
2017-02-25 10:40:56 -08:00
6f1a498ab9
Use DCSR constants from the debug spec.
...
Replace the constants with the ones from the ISA spec, since those are
not updated as often.
Also delete a bunch of old code.
Change-Id: I9201b1455d64a9d2d203bb362fefaa68cbf35aeb
2017-02-25 10:34:46 -08:00
8f6ddc92e8
Update bits to latest spec.
...
Change-Id: Ib09e1da81c6c0e7c9c6b69e9fe31eda20e3cd6e0
2017-02-25 10:17:27 -08:00
3bd661b679
Speed things up by ignoring return values.
...
The remote bitbang implementation is really slow when reading back data.
During many operations, like writing a block of memory, we don't need to
see the return data. By communicating this to the lower layers, we get
huge speedups. Downloads to spike now are 295KB/s.
That means the gdbserver.py download test now runs to completion,
unfortunately it fails. Everything else is still passing, though, so I'm
committing this change.
Change-Id: I44cc9db1ade0908c1a12d09b23fc8e529a802d88
2017-02-22 16:04:36 -08:00
f9168b09d0
Optimize memory write code, used in download.
...
To spike now we download at 5KB/s. But in real hardware performance
should be pretty OK now.
Change-Id: Ie6086cf156c9a00ac55400870346e27b28e3c755
2017-02-21 20:31:50 -08:00
4e8cf4aeb5
Better error checking in memory access.
...
Change-Id: I985afa433a09f833137f2e244b7eaad2630f6b1a
2017-02-20 17:53:18 -08:00
aba0c0973d
Properly restore s0 and s1 on resume.
...
Now 33/39 of the gdbserver tests pass!
Change-Id: I0cb38fbbcdc2c037ff0ec77229e79f24fa021663
2017-02-20 15:47:31 -08:00
3173314f28
Fix access FPU registers again.
...
Not a great fix. There's still a problem with accessing 64-bit floating
point registers on 32-bit cores.
24 of the gdbserver.py tests pass now.
Change-Id: I69a88ef5fd5581e2c7bf1d78057fd474ae86ff93
2017-02-17 19:03:32 -08:00
071f9a2916
Fix use of REG vs CSR constants.
...
23 gdbserver.py tests pass now.
Change-Id: I32805d615ae5f536f179baf906e0e74a56e80c0b
2017-02-17 12:35:43 -08:00
b363d1a37e
Bunch of register access refactoring.
...
Got rid of the last reference to the old debug RAM code! (Mostly?)
SimpleF18Test passes now.
Change-Id: Iab51d436a50bec9a5e504df7fb3cd6be874da0be
2017-02-17 11:53:37 -08:00
88f14f4d5e
Check busy before triggering another command.
...
This version was able to download code, and run to a breakpoint.
Change-Id: I0ead8350579263d8e55f8df35e2b7af6c374ef21
2017-02-16 14:21:17 -08:00
ef3875a320
Check for errors after read/write.
...
The code doesn't do anything intelligent if errors are found.
But MemTestBlock now also passes. I'm not quite sure why.
Change-Id: I8512f0a96db9e34d3db6a4a9bcef6e56f191d4c1
2017-02-15 20:41:39 -08:00
035b4dd17a
Fix double read, which might have side effects.
...
Now passing MemTest{8,16,32,64}
Change-Id: I286d1e2a388d41853e5aa9049490ddb6135b61f1
2017-02-15 19:05:51 -08:00
713c001242
Make MemTest32 pass.
...
Change-Id: I9be90b07be695c976380f9fd50b971f8bb94f513
2017-02-15 17:10:53 -08:00
79e840aaa7
Some memory access works.
...
MemTest16 passes, but MemTest32 fails.
Change-Id: I17fbc38b4228b27c7fb3dadb15e9c1a2f67bcd65
2017-02-15 15:44:36 -08:00
657e844c8c
Merge pull request #15 from sifive/get_set_reg_error
...
Use the set/reg register error return code when registers don't exist.
2017-02-14 17:28:10 -08:00
ceb8dc048d
Make general CSR reads work.
...
Change-Id: Ic9b7e065b7303b3707c28c9b7c496cc1c1e91acd
2017-02-14 12:55:03 -08:00
ae4fda2719
Make it all the way through examine().
...
This includes reading GPRs (although I haven't confirmed the values) and
doing some CSR reading/writing to disable triggers that may be left over
from a previous setting.
Change-Id: I2c627bd002d601e302a40f838087541897c025fd
2017-02-14 11:43:58 -08:00
00925574d5
More dbus->dmi.
...
Change-Id: Ia691f1e7ce909da4d9c16e6d691c4f2cf768a7fb
2017-02-14 09:38:09 -08:00
24033b53d8
Read misa during examine(), using program buffer.
...
Change-Id: Icad5324d216b61207cb5f6024b2deab065658640
2017-02-13 21:29:02 -08:00
0fa8162a8c
dbus -> dmi
...
Change-Id: I4c3343f8f5ffd45e3d76a2218aaa5dee8e546839
2017-02-13 11:13:14 -08:00
e2a5e02d1c
Discover XLEN using abstract reg reads.
...
Change-Id: Ib7480b8e4925cf08e5b59d263bcdcc672a89dc4b
2017-02-13 09:54:05 -08:00
e6221e75c9
Attempt to discover XLEN with abstract reg reads
...
Change-Id: I7ce9c8c0c34bd875dba11596e6f6268320b2fb3a
2017-02-10 19:08:44 -08:00
3a1d6f1702
riscv: Add register name to message when they do not exist.
2017-02-10 14:19:23 -08:00
5e3d9803ab
Halt target in riscv_examine().
...
Change-Id: I11ab915901f2e75f9b728d6cf72c6498e3950ded
2017-02-10 11:31:14 -08:00
075c0e80d1
Add debug_defines.h.
...
Change-Id: I94753f9bed11cbc978daa0f3ea3ecf2023b93893
2017-02-09 09:57:54 -08:00
2ad366e658
Detect and smoketest data and ibuf registers.
...
Change-Id: I7ee4817ec63041a1577b83392d40b676fb67c207
2017-02-08 20:40:37 -08:00
8cac7d0cee
Correctly parse dmcontrol.
...
Change-Id: Ibae425f4ccbe9e504c41e185f264f667e091fca4
2017-02-08 19:47:34 -08:00
8af4a9a053
Update DMI bus width for 0.13.
...
Change-Id: Ieff13a7a0084fe822b7cc6d927727eba4f158ef0
2017-02-07 11:28:50 -08:00
7b95554ff5
Merge remote-tracking branch 'origin/riscv' into HEAD
2017-02-07 11:24:12 -08:00
d78ee9303e
Merge pull request #16 from sifive/0.13
...
Refactor code to support multiple debug spec versions.
2017-02-06 09:20:15 -08:00
ecc5b6ecad
Add missing header file.
...
Change-Id: I19df5112c2503ec6652f2d09e7324180af5024df
2017-02-05 21:32:44 -08:00
2ae0078fc7
Use the set/reg register error return code when registers don't exist.
2017-02-05 21:06:43 -08:00
6f78eb1ec1
Add the first difference for 0.13 targets.
...
Just to confirm the 0.13 code takes a different path.
Change-Id: I7f1c9c8f3b586aee001dbeef2213f5f2e6a94f36
2017-02-05 18:21:34 -08:00
8d195afd2d
Use the csrNNN name instead of "mstatus".
...
Fixes flashing code.
Change-Id: Id12c926f5ada009e06f6601362deefec946afc98
2017-02-05 18:19:00 -08:00
d055f86552
Most gdbserver tests pass now.
...
Change-Id: I14a8360d9cf2800ca5e6a44f7e58102b2baef719
2017-02-05 18:09:19 -08:00
9bab0782d3
Merge pull request #13 from sifive/disable_interrupts
...
riscv: Globally disable interrupts when running algorithms.
2017-01-26 10:45:13 -08:00
5d82a395f1
riscv: disable interrupts for all priviledge levels
2017-01-25 21:51:02 -08:00
d5892f0ee5
riscv: Use proper UINT packing and unpacking routines for disabling interrupts before running algorithms.
2017-01-25 15:23:10 -08:00
5766efe0c3
riscv: Globally disable interrupts when running algorithms.
2017-01-25 11:35:57 -08:00
Megan Wachs
Palmer Dabbelt
Tim Newsome