Commit Graph

11551 Commits

Author SHA1 Message Date
Tim Newsome 2d4c53b338 jtag/drivers/xds110: Initialize `written`
Otherwise I get a compiler warning, which fails the build.

Change-Id: Ib7d4ab85160b537d07c74f8651ac42906fd661ed
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-20 09:22:27 -07:00
Tim Newsome 5d1b50af52
Merge pull request #866 from riscv/semi_magic
target/riscv: Early exit magic sequence checks in riscv_semihosting
2023-06-16 09:42:59 -07:00
Tim Newsome ebfd43c84f target/riscv: Early exit magic sequence checks in riscv_semihosting
When halted we don't need to read all 3 instructions before deciding the
sequence doesn't match.

Change-Id: I9f8345960ce27e859265af901a368166a70b9fde
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-15 10:40:37 -07:00
Chao Du c6e0716ac9
rtos/FreeRTOS: pxCurrentTCB should be used for judgment. (#862)
* rtos/FreeRTOS: pxCurrentTCB should be used for judgment.

The current TCB is stored in pxCurrentTCB, which is somehow RISC-V-specific, should not be overwritten from upstream (#816).

* fix the code style check.

Signed-off-by: Chao Du <duchao@eswincomputing.com>
Change-Id: I9ffa8947f0cb9e93c7d96866882a5a1e8e69afad

* revert some over-changes in last commit.

Change-Id: Ie88bd75b59190503db11ee4538281bd13b554e50
Signed-off-by: Chao Du <duchao@eswincomputing.com>

---------

Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-06-14 11:39:21 -07:00
Tim Newsome 8f81655256
Merge pull request #864 from riscv/prototypes
target/riscv: Remove unnecessary prototypes.
2023-06-12 09:00:22 -07:00
Tim Newsome 166b68c1b0 target/riscv: Remove unnecessary prototypes.
These functions used to exist but don't anymore. (Pointed out in #863)

Change-Id: Iac6b5edd320bdff7628a788861e332f956dcd93d
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-09 15:13:44 -07:00
Tim Newsome 973c72887c
Merge pull request #860 from riscv/examine_state
target/riscv: set_dcsr_ebreak() while target->state is still changed
2023-06-08 09:10:55 -07:00
Tim Newsome c8d6ffa6f0
Merge pull request #858 from MarekVCodasip/register-cache-invalidate
Add register cache flushing and invalidation to protobuf execution.
2023-06-08 09:04:54 -07:00
Tim Newsome ad89d570e7 target/riscv: set_dcsr_ebreak() while target->state is still changed
Otherwise it fails.

Fixes #859.

Change-Id: Ib59e6d840316b881481a9b1e01f9d546e73bf932
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-07 09:49:58 -07:00
Marek Vrbka 711ac4f0f0 target/riscv: add register cache flushing and invalidation to protobuf execution.
Previously, progbuf execution did not flush or invalidate the register cache which could lead to incorrect behavior. This patch fixes it as well as refactors few sore points in the code related to it.

Change-Id: I353b931ca70a1828d4a9cc512aead00441730875
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-06-07 09:41:30 +02:00
Tim Newsome e0dd44a53c
Merge pull request #856 from riscv/select_hart
target/riscv: Select hart in update_dcsr()
2023-06-06 08:56:05 -07:00
Tim Newsome 0ab2ebd191 target/riscv: Select hart in update_dcsr()
Otherwise we may end up modifying DCSR of a different hart than
intended.

Change-Id: I39bde21a1444623ed150f2b3d504b9318b9d6191
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-06-05 09:39:14 -07:00
Tim Newsome 5a9654d272
Merge pull request #854 from en-sc/en-sc/fix-regacc-running
target/riscv: fix register access on running target
2023-06-02 08:25:07 -07:00
Evgeniy Naydanov 3a29542056 target/riscv: fix register access on running target
Register access on running target should fail if mstatus needs to be
modified.

Change-Id: Iec8e8d514ef2f5ca42606a5534cce55aaaa99180
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-31 22:22:53 +03:00
Tim Newsome 58b6a5eabf
Merge pull request #851 from riscv/power_dance
target/riscv: Handle harts powering down and coming back up.
2023-05-30 12:51:24 -07:00
Tim Newsome f0898155d1 target/riscv: Set dcsr.ebreak* during examine()
This way if you connect to a running target, before it's hit a breakpoint,
then when it does hit the breakpoint OpenOCD will catch it.

Change-Id: I6f1e5f169fa385f46759015786e664693c3872e4
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:01:47 -07:00
Tim Newsome 21433e83ee target: poll() failure does not mean the target halted.
Poll failure just means poll failed. It's safer to assume the target is
still running, because then if it is running and subsequently halts we can
relay this to gdb correctly. We can't do the other way around, because once
gdb thinks the target has halted, it can't deal with it spontaneously
running.

Change-Id: Idb56137f1d6baa9afc1b0e55e4a48f407b8ebe83
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Tim Newsome 82ed02f92a target/riscv: Always clear progbuf cache in examine().
When a DM was powered down, we end up in examine() again, and clearly if
the DM was powered down we need to invalidate that cache.

Change-Id: I5eb6a289939f313e06c09cac22245db083026aa3
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Tim Newsome 1c5cf8023c target/riscv: Reset DTM when it reports an error.
The error state is sticky, so this has to be done to recover.

Change-Id: I589f3cdab0f2351fd25f89951830cbc16c39bd93
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-26 13:00:13 -07:00
Tim Newsome c8e7e3535c
Merge pull request #842 from en-sc/en-sc/optimize-access
target:riscv: optimize register accesses
2023-05-25 09:34:49 -07:00
Evgeniy Naydanov 5a29a7399f target/riscv: refactor register accesses
Change-Id: I45731d501f6261c4142c70afacf3fbbe42cf2806
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-23 20:20:19 +03:00
Evgeniy Naydanov c822dc8194 target/riscv: improve register caching (prep_*, cleanup_*)
Introduce riscv_write_register to prep_for_register/vector_access and
cleanup_after_register/vector_access.

Change-Id: I77a0a06ac6f12eceec309f0aff94aa77bd56ff55
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 8f3a617dc7 target/riscv: improve register caching (riscv_write_register)
This commit introduces a new function, which can be used to reduce number
of register accesses.

Change-Id: I125809726eb7797b11121175c3ad66bedb66dd0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 7a181e8bbc target/riscv: use `riscv_reg_t` and `enum gbb_regno` consistently
Change-Id: Ia476251e835fa5fd129ae6b679c6049c5c60c716
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 919a98a05b target/riscv: fix register cache flushing
Since writing a register can make some GPRs dirty (e.g. S0, S1), registers
should be flushed in reverse order, so GPRs are flushed last.

Change-Id: Ice352a4df4ae064619c0f9905db634a7b57e4711
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-05-22 11:55:37 +03:00
Jan Matyas 431deec8c9
Multiple improvements to Spike smoke-test workflow (#809)
* Multiple improvements to Spike smoke-test workflow

These changes have been made:

- use checkout action v3 (not v2) - silences a Github warning
- cache dependencies to speed-up the process (Spike + toolchain)
- reorder actions so that cached items are handled first
- move dependencies to /opt/riscv for easier caching
- archive logs from the tests (downloadable artifact)
- more descriptive names for some steps
- changed 'apt' to 'apt-get' to supress a warning

Change-Id: I5b8e9200c5d8cbaa3116bac565e009089bb6b36b
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

* Split cache for spike and toolchain

Change-Id: I423c4ba28e44ec5126786897135fb245e164c664
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

* Split cache for spike and toolchain - fix cache keys

Change-Id: I907bdb52f402b17a7829ea1d06cd395518de4cd3
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

* Empty commit to re-trigger the CI

Change-Id: I749d44d8f0dde09ce5adf6e2e1ab5a5324f4018f
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

---------

Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Co-authored-by: Jan Matyas <jan.matyas@codasip.com>
2023-05-18 14:15:54 -07:00
Tim Newsome 461eb65e21
Merge pull request #847 from riscv/data1_cache
target/riscv: Comment that data1 might change.
2023-05-18 10:56:00 -07:00
Antonio Borneo e17fe4db0f pld: validate exported functions by including its own .h
Let source files to include its file .h to validate the exported
prototypes.

Detected through 'sparse' tool.

Change-Id: I217c2903fdb19e1a2cce39d2536a903c3d72f3f7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7664
Tested-by: jenkins
2023-05-18 10:08:15 +00:00
Antonio Borneo 177bafd4cc pld: move in pld.h the pld_driver's declaration
The static analyser 'sparse' complains, while compiling a pld
driver, that the struct pld_driver is declared in the file as
non static, but it is not exposed through an include file.
The message is:
	warning: symbol 'XXX' was not declared. Should it be static?

Move the list of pld_driver's declaration in pld.h

Change-Id: I0f917aecc7534c1b51af0afa9b32ccfd33db3511
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7663
Tested-by: jenkins
2023-05-18 10:07:58 +00:00
Antonio Borneo 20005eb81a nor: move in driver.h the flash_driver's declaration
The static analyser 'sparse' complains, while compiling a nor
driver, that the struct flash_driver is declared in the file as
non static, but it is not exposed through an include file.
The message is:
	warning: symbol 'XXX' was not declared. Should it be static?

Move the list of flash_driver's declaration in driver.h
Fix some incorrect non-const declaration and remove redundant
forward declarations.

Change-Id: I5e41d094307aac4a57dfa9a70496ff3cf180bd92
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7662
Tested-by: jenkins
2023-05-18 10:07:34 +00:00
Antonio Borneo 5d77897526 nand: move in driver.h the nand_flash_controller's declaration
The static analyser 'sparse' complains, while compiling a nand
driver, that the struct nand_flash_controller is declared in the
file as non static, but it is not exposed through an include file.
The message is:
	warning: symbol 'XXX' was not declared. Should it be static?

Move the list of nand_flash_controller's declaration in driver.h
While there, drop the unused/commented boundary scan controller.

Change-Id: I7dc32cef55be13ba537abe0f4c47b135d837126c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7661
Tested-by: jenkins
2023-05-18 09:56:30 +00:00
Antonio Borneo f07efff961 rtos: move in rtos.h the rtos_type's declaration
The static analyser 'sparse' complains, while compiling a rtos'
file, that the struct rtos_type is declared in the file as non
static, but it is not exposed through an include file.
The message is:
	warning: symbol 'XXX' was not declared. Should it be static?

Move the list of rtos_type's declaration in rtos.h

Change-Id: Ia96dff077407a6653b11920519c1724e4c1167a3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7660
Tested-by: jenkins
2023-05-18 09:55:48 +00:00
Antonio Borneo ed46188a72 target: move in target_type.h the target_type's declaration
The static analyser 'sparse' complains, while compiling a target's
file, that the struct target_type is declared in the file as non
static, but it is not exposed through an include file.
The message is:
	warning: symbol 'XXX' was not declared. Should it be static?

Move the list of target_type's declaration in target_type.h
While there, fix a name clash in stm8.c

Change-Id: Ia9c681e0825cfd04d509616dbc04a0cf4944f379
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7659
Tested-by: jenkins
2023-05-18 09:54:59 +00:00
Tim Newsome be5187d0a8 target/riscv: Comment that data1 might change.
In case in the future I have the same idea of optimizing progbuf writes
again.

Change-Id: Ie383487691cceeff75e2c22f4c85fc1fe4873937
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-17 09:46:23 -07:00
Tim Newsome 0a38258f71
Merge pull request #848 from riscv/removed-unused-func-set-frontend-running
gdb_server: Removed unused function gdb_set_frontend_state_running
2023-05-16 09:28:14 -07:00
Tim Newsome d78d991191
Merge pull request #850 from riscv/cleanup-in-target-c
Minor cleanup in target.c
2023-05-16 09:27:57 -07:00
Tim Newsome 15bd33cc20
Merge pull request #844 from riscv/from_upstream
Merge 228fe7 from upstream
2023-05-15 08:17:31 -07:00
Jan Matyas bd275ef483 Minor cleanup in target.c
Small cleanup in target.c to get rid of few upstream differences:

- removed a pointless check for `reg->exists` - already checked
  few lines above
- unify one log message with what's in upstream

Change-Id: I3fd761157382670611fa90de84e2dfc90192f473
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-05-15 15:09:55 +02:00
Jan Matyas 528970c47a gdb_server: Removed unused function gdb_set_frontend_state_running
Non-functional change: unused function removed that does not exist
in the OpenOCD upstream, either.

Change-Id: Ibeab5b41a24183673cc02ca919b2f7285309e6f4
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-05-15 12:38:02 +02:00
Paul Fertser 3a4f445bd9 jtag: tcl: show error message when attempting manual "drscan" on a bypassed tap
To perform any meaningful manipulations with DR the corresponding IR should
be set to a relevant instruction, not BYPASS, so warn the user accordingly.

Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I42580ecd75ae824a4145f6f17f0df9bcf825b50f
Reviewed-on: https://review.openocd.org/c/openocd/+/7654
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-05-13 09:24:05 +00:00
Paul Fertser 8d12ae796e jtag: tcl: change drscan usage to show at least one value is required
It's customary to use [] brackets to mean the argument is optional, but
drscan requires at least one pair of "num_bits value" so change it to ().
In common regular expressions * means 0 or more, and + means 1 or more,
so change that too.

Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: Ib15d833bda2aa398ad1345a042f97d91c98dbf66
Reviewed-on: https://review.openocd.org/c/openocd/+/7653
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-13 09:22:31 +00:00
Antonio Borneo 85b5c51806 target: rewrite command 'arp_reset' as COMMAND_HANDLER
While there, add the missing .usage field and move in target.c the
enum nvp_assert.

Change-Id: Ia4f2f962887b5a35faeaa4eae128fa2865569b24
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7559
Tested-by: jenkins
2023-05-13 08:55:55 +00:00
Antonio Borneo b931286ab4 target: rewrite command 'arp_halt' as COMMAND_HANDLER
While there, add the missing .usage field.

Change-Id: I748382cafe08443c458ff1d4e47819610cfbf85c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7558
Tested-by: jenkins
2023-05-13 08:55:14 +00:00
Antonio Borneo 219412f9d6 target: rewrite command 'arp_poll' as COMMAND_HANDLER
While there, add the missing .usage field.

Change-Id: I16e0aeacdaaada09fa77ad29552fa4025eff0c45
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7557
Tested-by: jenkins
2023-05-13 08:54:37 +00:00
Antonio Borneo 7319eb3a25 jtag: rewrite command 'pathmove' as COMMAND_HANDLER
Change-Id: I1f8c6722021f392b1f065484b63a19964db69ad5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7556
Tested-by: jenkins
2023-05-13 08:53:51 +00:00
Antonio Borneo 4bf994fc9c jtag: rewrite command 'drscan' as COMMAND_HANDLER
Reorganize the code to parse the command line only once.
Add check for successful memory allocation.

Change-Id: Ibf6068e177c09e93150d11aecfcf079348c47c21
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7555
Tested-by: jenkins
2023-05-13 08:53:06 +00:00
Antonio Borneo 599f1cf763 openocd: trivial replace of jim-nvp with new nvp
For some trivial case only, replace calls to jim-nvp with calls
to the new OpenOCD nvp.

Change-Id: Ifd9aff32b67748af8ab808e6a6b6e64f5271b888
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7553
Tested-by: jenkins
2023-05-13 08:49:05 +00:00
Antonio Borneo 160288137a xtensa: fix build with gcc 13.1.1
New gcc does not understand that the variable 'restore_ms' is set
to 'true' only when the variable 'ms' is assigned in
	static int xtensa_write_dirty_registers(...)
	{
		xtensa_reg_val_t ms;
		bool restore_ms = false;
		...
		if (...) {
			ms = regval;
			restore_ms = true;
			...
		}
		...
		if (restore_ms) {
			USE(ms);
		}
		...
	}
and complains about possible use of uninitialized variable 'ms'.

Sadly initialize 'ms' to zero to hide this false positive.

Change-Id: I1fb3949070c8abbf4aa45a740f0ca2fdb753d4fa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7681
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Tested-by: jenkins
2023-05-13 08:47:27 +00:00
Tim Newsome e02c83e401
Merge pull request #846 from riscv/cleanup
target/riscv: Remove non-functional code in riscv_program_exec().
2023-05-11 10:27:46 -07:00
Tim Newsome 57d20e4d96 target/riscv: Remove non-functional code in riscv_program_exec().
Addresses #845.

Change-Id: If4eee383f92946669a84f92e52a3ac3600707525
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-05-10 16:58:09 -07:00