Megan Wachs
a81ad34af3
Merge pull request #148 from riscv/macbuild
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Use %ll instead of %L in scanf.
2017-12-21 15:16:57 -08:00
Tim Newsome
b01075eaa5
Merge pull request #145 from riscv/rbb_win
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Fix Windows build
2017-12-21 14:04:33 -08:00
Tim Newsome
105536089b
Merge pull request #151 from riscv/use_paren
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Use parens after if.
2017-12-21 12:50:56 -08:00
Tim Newsome
fa385bdcd5
Use parens after if.
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I'm surprised this built with gcc before.
Fixes Issue #150 .
Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
2017-12-21 12:43:22 -08:00
Tim Newsome
f13093fff7
Merge pull request #149 from riscv/xml_registers
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Send gdb an XML target description that contains only a list of registers we think exist on this target
2017-12-19 11:13:19 -08:00
Tim Newsome
11c261cd50
Add `riscv expose_csrs` command.
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This lets users tell OpenOCD which non-standard CSRs exist on their
target, that will also be accessible and whose existence will be
communicated to gdb.
Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
2017-12-19 10:41:48 -08:00
Tim Newsome
5f86f7208d
Hide supervisor registers if there is no S mode.
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Also update encoding.h.
Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
2017-12-19 10:41:48 -08:00
Tim Newsome
f55d1a2030
Give FPRs ABI names.
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Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
2017-12-19 10:41:48 -08:00
Tim Newsome
c7cddd2b5c
Remove some debug printfs.
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Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
2017-12-19 10:41:48 -08:00
Tim Newsome
56ad0e5b30
Avoid another assertion failure.
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Change-Id: Ia54f778152974164697b712c360918e17a127d95
2017-12-19 10:41:48 -08:00
Tim Newsome
10c17fdf17
Read misa before using it to check for extensions.
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Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
2017-12-19 10:41:48 -08:00
Tim Newsome
ec1c814017
Don't rely on hart count until it's correct.
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Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
2017-12-19 10:41:48 -08:00
Tim Newsome
46715c7d8a
Remove no-longer-true comment.
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Change-Id: I888680e73682582438a0de0496238867f1604754
2017-12-19 10:41:48 -08:00
Tim Newsome
120477b2a2
Simplify examine()
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Now we don't have to play tricks fooling other parts of our code that
might assert.
Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
2017-12-19 10:41:48 -08:00
Tim Newsome
37278cf2ec
Make priv register 8 bits.
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(It's really only 2 bits, but something wonky happens between gdb and
OpenOCD if I make it that size.)
Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
2017-12-19 10:41:48 -08:00
Tim Newsome
f341db9f72
WIP xml register for 0.11.
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On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.
Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19 10:41:48 -08:00
Tim Newsome
8926e66d3a
Hide unknown registers, which probably don't exist
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Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
2017-12-19 10:41:48 -08:00
Tim Newsome
26a54452d2
Fix register names.
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Use the ABI ones for every register that we have one for.
Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19 10:41:48 -08:00
Tim Newsome
7c989698a1
WIP better CSR names, and include only existing
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Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
2017-12-19 10:41:48 -08:00
Tim Newsome
a5cb0b2270
WIP. Hide FPRs if the hart doesn't support F/D.
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Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
2017-12-19 10:41:48 -08:00
Tim Newsome
e648856a41
`make all` debug tests now pass.
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Also properly support (I think) D extension on RV32.
Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
2017-12-19 10:41:48 -08:00
Tim Newsome
c421fefdcb
Checkpoint that seems to work.
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Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
2017-12-19 10:41:48 -08:00
Tim Newsome
1e43d32e01
Use %ll instead of %L instead of scanf.
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Mac build barfs on L, and the manpage says they're equivalent.
Hopefully fixes #147
Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
2017-12-15 15:31:36 -08:00
Tim Newsome
b8db82fb57
Merge pull request #146 from riscv/scratch_ram
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Fix cut and paste bug.
2017-12-14 14:22:10 -08:00
Tim Newsome
6aff46adcc
Fix cut and paste bug.
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Now reading 64-bit FPRs on 32-bit harts using scratch memory might work.
Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
2017-12-14 13:51:13 -08:00
Tim Newsome
7eceac758c
Use abstraction because Windows is not POSIX
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Fixes #138
Change-Id: I4d9b49762e318fe91f1561ed315829b43daefef4
2017-12-14 12:36:42 -08:00
Tim Newsome
3624d5e5eb
Add win32 build to travis.
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Change-Id: I8ce62ff321c6f3627d42fff13236f7fc9440d429
2017-12-14 12:36:21 -08:00
Tim Newsome
20236ca817
Merge pull request #143 from riscv/fmv
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Fix build.
2017-12-11 13:07:35 -08:00
Tim Newsome
0a65a6527d
Fix build.
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Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
2017-12-11 12:58:20 -08:00
Tim Newsome
e50ee46a6f
Merge pull request #131 from riscv/small_progbuf
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Support program buffers that are just 2 instructions large
2017-12-11 12:52:31 -08:00
Tim Newsome
7a6704c5c6
Merge pull request #140 from riscv/encoding
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Update encoding.h.
2017-11-27 13:48:56 -08:00
Tim Newsome
4d5f74fbe6
Update encoding.h.
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Change-Id: Id653500aa525746e8824ff5fd2850c62c8c21c08
2017-11-27 13:23:33 -08:00
Tim Newsome
52cdf286ca
Add missing return.
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Change-Id: Ida32482903cdfd8eeb043088e84bb1f4f5ac673c
2017-11-16 15:58:08 -08:00
Tim Newsome
9b4628c9fc
Merge pull request #127 from riscv/jtag_debug
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Clean up this JTAG debug code.
2017-11-14 09:59:25 -08:00
Palmer Dabbelt
055a70f66f
Merge pull request #133 from riscv/no-russian
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No Russian
2017-11-03 13:15:07 -07:00
Tim Newsome
e28abf7c9e
Merge branch 'riscv' into small_progbuf
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Change-Id: I1d48cb1f8448ebbf98c8bb369928d1e7a7a78c75
2017-11-01 13:38:17 -07:00
Tim Newsome
8304e1ba47
Merge pull request #134 from riscv/compile
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Fix compile warning with gcc 6.3.0
2017-11-01 11:04:23 -07:00
Tim Newsome
40c97cc476
Merge pull request #135 from riscv/fuller_build
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Build OpenOCD the way we expect users to build it.
2017-11-01 10:54:52 -07:00
Tim Newsome
a4472f6d66
Build OpenOCD the way we expect users to build it.
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Change-Id: I3769137bc3109b44da76f2ca689d351bb93e7832
2017-10-31 13:21:37 -07:00
Tim Newsome
6a1690d2ec
Fix compile warning with new gcc.
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Change-Id: I14ebf597f41429c0fc3ebac8da9c9f62c78fb1ae
2017-10-27 13:42:39 -07:00
Tim Newsome
db754536e8
Support 64-bit FPRs on RV32.
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Because there is no instruction that moves just half of a 64-bit FPR
to/from a GPR, we need to use scratch memory for this operation. This
code can theoretically use:
1. DMI_DATA, if it is memory mapped in the target.
2. DMI_PROGBUF, if it is writable in the target.
3. A user-configured address.
I have only tested this code very lightly. One reason is that gdb thinks
that on RV32 harts every register is 32 bits wide. Another is that this
is mostly proof-of-concept to satisfy the small program buffer code
review, which I don't want to drag out forever.
Existing tests don't realize that floating support was broken with
RV32D, and don't realize that it still doesn't work because of the gdb
problem mentioned above.
This change improves Issue #110 but there's more work to be done.
Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
2017-10-27 13:15:22 -07:00
Palmer Dabbelt
6ba66c9503
No Russian
2017-10-26 09:32:34 -07:00
Tim Newsome
f416527985
Merge pull request #132 from riscv/cleanup
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Remove unused variables.
2017-10-26 08:14:31 -07:00
Tim Newsome
1acb128290
Remove unused variables.
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Change-Id: I678d0a65c22792895375dc6916381f81af8f83e4
2017-10-25 13:37:56 -07:00
Tim Newsome
23bd6d08c9
Remove more unused functionality.
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Change-Id: I43283b9556c959f891a587fb39bdd1ab9206e8af
2017-10-24 15:11:33 -07:00
Tim Newsome
dbecbfee99
Add a fence after memory writes.
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Change-Id: I5137479b685f735aa573cec5d40170016c40f597
2017-10-24 12:15:25 -07:00
Tim Newsome
59a0340261
Remove more unused code.
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Change-Id: I962660f58d948f85df6e073065e15e5d8f4a02b6
2017-10-24 11:38:39 -07:00
Tim Newsome
8432b7cf3d
Remove more unused code.
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Change-Id: Id91237c163d86e8f4d039503ca33b4ad7571ecd1
2017-10-24 11:34:48 -07:00
Tim Newsome
3ba6d46fc2
Remove unused functionality.
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Change-Id: Ic70cebd62bbd04f7ae5566504fbb279a11de57f0
2017-10-23 14:45:58 -07:00
Tim Newsome
5425c871c9
Properly fix memory read when encountering busy.
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Change-Id: I377054495e860076edc2f38d1cc0f11c23f98d3b
2017-10-23 14:13:46 -07:00