Commit Graph

207 Commits

Author SHA1 Message Date
Tim Newsome 874cadca31
Conform to OpenOCD style. (#323)
Change-Id: I11b5b66e474d3e1d979b4db537363d025f8e2c9a
2018-11-05 12:27:56 -08:00
Pavel S. Smirnov 60368dd62e FIX(src/target/riscv/riscv.c): riscv_add_breakpoint: RVC: invalid 32bit transactions size for 16bit aligned instruction (#322) 2018-11-05 11:34:44 -08:00
Carsten Gosvig dc4fe85880 Old fixes from June (#311)
* Changed logging level

* Added logging statement

* Removed halt event when attaching to target

* Extended some packet handling

* Extended handling of rtos_hart_id and clearing of register cache

* Extended execute_fence to handle all harts

* Removing logging statement again

* Updated according to review comments

* Forgot to re-add the return statement

* Was removing too much for the if statement to work

* This needs to >= 3 now to handle both a fence and a fence.i
2018-10-30 11:29:00 -07:00
Tim Newsome e54511ffa4
Revert "Don't report exact watchpoint to gdb. (#300)" (#304)
This reverts commit 933cb875a8.

https://github.com/riscv/riscv-openocd/issues/295 was fixed in gdb.
2018-10-24 13:02:44 -07:00
Tim Newsome b986d29bc9
Fix segfault in riscv_deinit_target(). (#306)
This would happen when OpenOCD is unable to connect to the JTAG device.

Change-Id: I1785fd5f5a20db9b4b574bdddfe3eab9bdc0b0bc
2018-10-18 10:06:23 -07:00
Tim Newsome 933cb875a8
Don't report exact watchpoint to gdb. (#300)
We should have a fix for #295 first.

Change-Id: Ic72a7a3fa866fbb5aaed22689adfebf9ce913b50
2018-09-06 15:39:25 -07:00
Megan Wachs 4b29af433d Merge remote-tracking branch 'origin/riscv' into sba_tests 2018-08-31 09:02:55 -07:00
Tim Newsome a0afcba66d
Fix typo. 2018-08-29 16:05:54 -07:00
Tim Newsome 164415cfbe
Merge branch 'riscv' into sba_tests 2018-08-29 15:55:30 -07:00
Megan Wachs 34ee883aef Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebase 2018-08-29 15:47:54 -07:00
Tim Newsome b4b2ec7d2d
Add command to expose custom registers (#293)
* Added `riscv expose_custom` command.

Seems to work for reading. I need to do some more testing for writes, as
well as minor cleanup.

Change-Id: I85d5d00897d5da4add4a6643b538be37d31a016f

* Conform to OpenOCD style.

Change-Id: I40a316f06f418d2b63d9e11aea03ef51da8d8faf

* Free all the memory allocated by register init.

Change-Id: I04e35ab54613f99708cee85e41fef989079adefc

* Properly document `riscv expose_custom`.

Change-Id: Id78a02b7a00c161df80f11b521a306e0cf3d7478
2018-08-29 14:22:50 -07:00
craigblackmore 7897d40099 Handle hardware watchpoints hit by RV32 loads and stores (#291)
* Add riscv_hit_watchpoint function for RV32I loads and stores

For GDB to fully support hardware watchpoints, OpenOCD needs to tell GDB
which data address has been hit. OpenOCD relies on a target-specific
hit_watchpoint function to do this. If GDB is not given the address, it
will not print the hit variable name or its old and new value.

There does not seem to be a way for the hardware to tell us which trigger
was hit (0.13 introduced the 'hit bit' but this is optional). Alternatively,
we can decode the instruction at dpc and find out which memory address
it accesses.

This commit adds support for RV32I load and store instructions
and could be extended for additional instructions in the future.

* 0.11: change debug reason for hw triggers to DBG_REASON_WATCHPOINT

This is to make sure riscv_hit_watchpoint is called to check for a data
address hit.

* Fix style issues

* Change %lx to PRIx64 to clear -m32 build errors

* Add clarifying comments/todos

* Fix types in format strings
2018-08-27 12:42:34 -07:00
Dmitry Ryzhov f54eaf0b8e Switch active rtos thread on any hart halt. (#290) 2018-08-23 16:52:12 -07:00
Tim Newsome ead2a595b8 Use work area instead of riscv-specific config
Per review requested at http://openocd.zylin.com/#/c/4578/3

Change-Id: I1a8117665d38844dc1479f33b4f9b7c8f9f101c8
2018-07-16 14:43:15 -07:00
Liviu Ionescu 45921eecd8 target/riscv: fix trailing spaces 2018-06-12 23:58:56 +03:00
Liviu Ionescu 8022a315a6 target/riscv: explain why `arm` commands are used 2018-06-12 23:54:41 +03:00
Liviu Ionescu 08a814686d target/riscv: add semihosting support
- use the semihosting_common code
- to enable it, use the same commands as for arm

Signed-off-by: Liviu Ionescu <ilg@livius.net>
2018-06-12 18:21:01 +03:00
Tim Newsome ab7ab8a867
Merge pull request #261 from riscv/trigger_enum
Delay trigger enumeration until it's required.
2018-05-25 11:52:10 -07:00
Megan Wachs bdc4355493 Merge remote-tracking branch 'origin/trigger_enum' into riscv-compliance 2018-05-22 16:27:52 -07:00
Megan Wachs a0e811580a Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-22 16:27:29 -07:00
Tim Newsome c3ffbc66e6
Merge pull request #257 from riscv/comment
Comment riscv_set_register, register_write_direct
2018-05-22 14:39:28 -07:00
Tim Newsome b629bbeade Delay trigger enumeration until it's required.
This improves startup time, which is important when connecting to
simulators. One problem is that triggers that are set when the debugger
connects are not cleared until enumeration happens. Execution may halt
due to a trigger set by a previous debug session, which could confuse
the user. If this happens, triggers will be instantly enumerated, so it
will only happen once per session.

Change-Id: I3396f713f16980a8b74745a1672fe8b8a2d4abae
2018-05-22 13:07:25 -07:00
Dan Robertson 0493ff81a1
Fix posible null deref in get_target_type
A null deref occurs if riscv_deinit_target is called and the
target has not been initialized.

Change-Id: Ic34057508ed6686eb48e9fe8220110c42ba2fc5e
2018-05-22 02:57:16 +00:00
Tim Newsome 0ad060d97a Review feedback.
Change-Id: If58c011fc8d89d329d65a6c624ffb631f111cef2
2018-05-17 18:08:08 -07:00
Tim Newsome 41c42bf2df Comment riscv_set_register, register_write_direct
Fixes #241

Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
2018-05-17 18:01:00 -07:00
Megan Wachs efd7260972 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-14 07:31:25 -07:00
Tim Newsome dabaf170ba blank_check_memory prototype has changed.
Just remove our nop implementation. The default behavior when this is
left NULL does the same thing.

Change-Id: I865976c694d24661941584cb0efc92fc26612316
2018-05-08 15:21:49 -07:00
Tim Newsome 2a103bae44 Don't error if hart select isn't implemented.
It's not implemented for 0.11 because we don't need it. Returning error
caused 0.11 targets to not be debuggable since change
848062d0d1.

Change-Id: I8b04a1fcf3c3e8bf8340cbf39aaf475d2a213519
2018-05-07 15:16:57 -07:00
Tim Newsome 67b4e2c522 counter*h registers only exist on RV32
Fixes #245.

Change-Id: If05ec9773dc9975931434f09c431eba122a6e8d0
2018-05-03 12:26:30 -07:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Megan Wachs 3fedb7d97f Merge remote-tracking branch 'origin/riscv' into HEAD 2018-04-18 15:22:38 -07:00
Tim Newsome 69a426038d
Enforce OpenOCD style guide. (#239)
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
2018-04-18 13:11:08 -07:00
Megan Wachs 6217f56186 Merge remote-tracking branch 'origin/notice_reset' into riscv-compliance 2018-04-17 15:47:41 -07:00
Megan Wachs bc32aaafa4 riscv-compliance: whitespace cleanup 2018-04-16 17:49:16 -07:00
Ryan Macdonald bf0ffff1db Fix issue with COMMAND_PARSE_NUMBER 2018-04-13 16:09:57 -07:00
Megan Wachs adf7dd7b5e Merge branch 'riscv' into riscv-compliance 2018-04-12 16:03:54 -07:00
Ryan Macdonald cc98a14839 Added address alignment test, code fixups from review 2018-04-11 14:26:16 -07:00
Ryan Macdonald c2c52c89b1 Fix some build issues 2018-04-09 11:38:41 -07:00
Ryan Macdonald 99f2f5a272 Change #ifdef SIM_ON to be a run-time arg 2018-04-09 11:26:31 -07:00
Ryan Macdonald a9b2277574 Add #ifdef to only enable sbbusyerror test in simulation. 2018-04-09 10:51:53 -07:00
Ryan Macdonald d471fff3db Fixed build issues 2018-04-05 17:57:53 -07:00
Ryan Macdonald 3bdb8b29a8 Checkpoint: finish debug of tests, working on hitting sbbusyerror case 2018-04-05 16:31:09 -07:00
Ryan Macdonald c5a8e1cf4c Initial commit of tests for SBA feature 2018-04-04 13:50:17 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
2018-04-03 15:12:19 -07:00
Tim Newsome eeae8c4261 Add gdb_report_register_access_error command
This replaces the earlier mechanism which would propagate errors only
for targets that decided they wanted to. It was suggested by Matthias
Welwarsky from the OpenOCD team.

Change-Id: Ibe8e97644abb47aff26d74b8280377d42615a4d3
2018-04-02 13:37:53 -07:00
Tim Newsome 3c7c7e26a4
Merge pull request #230 from riscv/deleg
Make m*deleg regs conditional on U/S/N
2018-03-30 14:02:13 -07:00
Tim Newsome 224e7b4f16 Once more... Less sloppy this time.
Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86
2018-03-27 11:42:32 -07:00
Tim Newsome 55e427b72b Don't rely on havereset when deasserting reset.
This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
2018-03-27 11:31:39 -07:00
Tim Newsome 0c05aafbf8 Fix m*deleg logic.
Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
2018-03-26 16:00:34 -07:00
Tim Newsome b6dca68b2e Make m*deleg regs conditional on U/S/N
Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84
2018-03-23 13:43:12 -07:00