This was used to track which hart a given operation must apply to. But
we already have a target associated with each operation, and from there
we can find the desired hart id. dm013_info_t already tracks
current_hartid (meaning which hart ID is currently selected by the DM).
This makes the code simpler to understand. Also it turns out we don't
need to make sure the correct hart ID is currently selected because
there are only a few real entry points.
Change-Id: Ibe8d5e156523397f245edd6ec0a5df3239b717bf
Signed-off-by: Tim Newsome <tim@sifive.com>
The segfault could be triggered if:
- At least one target failed to get examined (therefore does not have the
register cache set up yet),
- and "reset" TCL command was issued, which internally tries to
invalidate the register cache.
Minor cleanup: "registers_initialized" member removed from riscv_info_t
because it is not used anywhere.
Change-Id: I6288c0d4343ef6a330fb2a6b49d388e7eafa32a2
Signed-off-by: Jan Matyas <matyas@codasip.com>
This commit relates to progbuf cache,
implemented in https://github.com/riscv/riscv-openocd/pull/381
Make sure the cache gets invalidated when the progbuf
contents change via other means. I've identified two
such cases where the invalidation is required:
1) When the user manually tinkers with the progbuf registers
(TCL command "riscv dmi_write")
2) When program buffer is used as a scratch memory
(scratch_write64())
Change-Id: Ie7ffb0fccda63297de894ab919d09082ea21cfae
Signed-off-by: Jan Matyas <matyas@codasip.com>
This replaces a static array with 8 bytes per register. When there are
vector registers larger than 8 bytes, they would end up clobbering each
other's values. I can't believe I didn't catch this earlier.
Change-Id: I9df4eaf05617a2c8df3140fff9fe53f61ab2b261
Signed-off-by: Tim Newsome <tim@sifive.com>
This makes things work as expected when OpenOCD disconnects and then
connects again. (This became a problem in #645, which started using the
cache.)
Change-Id: I764e5b410a1a68ca47d2ec39968085618ee363c2
Signed-off-by: Tim Newsome <tim@sifive.com>
This primarily contains the large upstreaming of RISC-V changes, so lots
more RISC-V changes than usual.
Conflicts:
src/target/riscv/opcodes.h
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
Change-Id: I1145dad538a5470ad209848572e6b0f560b671e9
Signed-off-by: Tim Newsome <tim@sifive.com>
Made no attempt to separate this out into reviewable chunks, since this
is all RISC-V-specific code developed at
https://github.com/riscv/riscv-openocd
Memory sample and repeat read functionality was left out of this change
since it requires some target-independent changes that I'll upstream
some other time.
Change-Id: I92917c86d549c232cbf36ffbfefc93331c05accd
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6529
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* WIP on register caching.
So we don't have to save/restore S0 all the time.
Change-Id: I9d83a24dbd92a325213f2b25eebc9ede9dca2868
* Seems to work for RV32.
Change-Id: Ide620faa5dfef4f39c3146e094787ea28d041327
* Use caching everywhere.
Change-Id: I0de249437589e1f49811f34c12726528c045c74f
* Getting closer...
Change-Id: I532455f1e416723b79eecc7d33ec6407ccb8e33c
* All spike tests pass again.
Running all tests now takes 2m54s compared to 3m0s. That's probably not
the thing to measure, since the goal is to improve interactive
performance, while the tests do all kinds of other stuff (like sleep,
and start spike, etc.).
Change-Id: Ic7d944454a64b2baf6e6028debb4a1ba896834d8
* Save s0/s1 during examine.
Change-Id: I4795180e3b04d01433a11d4a0ccb38c35074cc44
Signed-off-by: Tim Newsome <tim@sifive.com>
* Check flush registers result.
Change-Id: I8350c4198cb41881e1143816698aed677a312111
Signed-off-by: Tim Newsome <tim@sifive.com>
* Fix upstream style regression.
Change-Id: I4cc7034151ba62fa51aea77e44b0cad9b9b97876
Signed-off-by: Tim Newsome <tim@sifive.com>
AFAIK there is no hardware that implements this, but it should be a
close-to-done starting point in case it is ever required.
Change-Id: I49e3082e8629b1d70b12e8a847c2848e75b04508
Signed-off-by: Tim Newsome <tim@sifive.com>
* Remove `-rtos riscv`.
`-rtos hwwthread` is target-independent and a cleaner way to achieve the
same thing.
Change-Id: I863a91f9ad66e37dc36f2fbcbffe403b91355556
* Little more cleanup.
Change-Id: I8fda2317368a94760bc734abc7f1de6ee5b82a7c
* Clean up some more.
Change-Id: I64a1e96aa3bd8c0561d4d19930f99e9bc40eab86
* Get rid of riscv_[sg]et_register_on_hart
Change-Id: I5ea9439bad0e74d7ed2099935e7fc7292c4a2b7f
* Remove hartid arg from set_register.
Change-Id: Ib560e3c63ff32191589c74d3ee06b12295107c6f
* Remove more references to hartid.
Change-Id: Ie9d932fb8b671c478271c1084dad43cad3b2bfbc
* Remove some unused code.
Change-Id: I233360c6c420d1fc98b923d067e65a9419d88d7b
Signed-off-by: Tim Newsome <tim@sifive.com>
Add `riscv info` command. Final output is "TCL format" and looks like this:
```
hart.xlen 64
hart.trigger_count 4
dm.abits 6
dm.progbufsize 2
dm.sbversion 0
dm.sbasize 0
dm.sbaccess128 0
dm.sbaccess64 0
dm.sbaccess32 0
dm.sbaccess16 0
dm.sbaccess8 0
```
* Add `riscv info` command.
This command displays some basic information that OpenOCD has detected
about the target. The output is displayed in YAML so it can easily be
parsed. Example of current output:
```
Hart:
XLEN: 32
trigger count: 4
Debug Module:
abits: 6
progbufsize: 2
sbversion: 0
sbasize: 0
sbaccess128: 0
sbaccess64: 0
sbaccess32: 0
sbaccess16: 0
sbaccess8: 0
```
Change-Id: If920c083ff6ec9f482c50f913cd8ceaa62461217
Signed-off-by: Tim Newsome <tim@sifive.com>
* Disable workflow inherited from upstream.
Change-Id: Ifc5ed1b4f5ec2278b8bcf3279c9fd462e469fefa
Signed-off-by: Tim Newsome <tim@sifive.com>
* Switch from YAML to TCL "set array" input format.
Change-Id: I3833210e5bf6d7cffc9934c04ec5201ae7732ad8
Signed-off-by: Tim Newsome <tim@sifive.com>
* Remove indent in `riscv info` output.
That was getting a little too cute, and probably more confusing than
helpful.
Change-Id: Ie51416f53ab4b69294962f0565767d370db82867
Signed-off-by: Tim Newsome <tim@sifive.com>
The use of 'void *' makes the pointer arithmetic incompatible with
standard C, even if this is allowed by GCC extensions.
The use of 'void *' can also hide incorrect pointer assignments.
Switch to 'uint8_t *' and add GCC warning flag to track any use of
pointer arithmetic extension.
Change-Id: Ic4d15a232834cd6b374330f70e2473a359b1607f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5937
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This lets a user see exactly what period of time was sampled, without
having to guess how much time the target was ignored in between bursts.
Change-Id: I5c0639528636bf1a88f249be3ba59bec28c001e2
Signed-off-by: Tim Newsome <tim@sifive.com>
* Allow riscv_semihosting without 16 bit access to memory with instrustions
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* rename *_by_any_size to riscv_*_by_any_size
Used histogram diff strategy, which was much better than the default.
Conflicts:
doc/openocd.texi
src/flash/nor/fespi.c
src/jtag/drivers/libjaylink
src/rtos/rtos.c
src/target/riscv/batch.c
src/target/riscv/encoding.h
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
src/target/target.c
tcl/target/gd32vf103.cfg
Change-Id: I1321f62ba719419e58f93b2195f2540bd62f50d2
These are all the changes from https://github.com/riscv/riscv-openocd
(approximately 91dc0c0c) made just to src/target/riscv/*. Some of the
new code is disabled because it requires some other target-independent
changes which I didn't want to include here.
Built like this, OpenOCD passes:
* All single-RV32 tests against spike.
* All single-RV64 tests against spike.
* Enough HiFive1 tests. (I suspect the failures are due to the test
suite rotting.)
* Many dual-RV32 (-rtos hwthread) against spike.
* Many dual-RV64 (-rtos hwthread) against spike.
I suspect this is an overall improvement compared to what's in mainline
right now, and it gets me a lot closer to getting all the riscv-openocd
work upstreamed.
Change-Id: Ide2f80c9397400780ff6780d78a206bc6a6e2f98
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/5821
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
* Add memory sampling feature.
Currently only gets 10 samples per second, but the overall scaffolding
looks like it works.
Change-Id: I25a2bbcba322f2101c3de598c225f83c902680fa
* Basic memory sample speed-ups.
977 samples/second.
Change-Id: I6ea874f25051aca1cbe3aa2918567a4ee316c4be
* Add base64 dumping of sample buffer.
We can't just dump raw data, because the API we use to get data to the
"user" uses NULL-terminated strings.
Change-Id: I3f33faaa485a74735c13cdaad685e336c1e2095f
* WIP on optimizing PC sampling.
1k samples per second on my laptop, which is roughly double what it was.
Change-Id: I6a77df8aa53118e44928f96d22210df84be45eda
* WIP
Change-Id: I4300692355cb0cf997ec59ab5ca71543b295abb0
* Use small batch to sample memory.
5k samples/second. No error checking.
Change-Id: I8a7f08e49cb153699021e27f8006beb0e6db70ee
* Collect memory samples near continuously.
Rewrite OpenOCD's core loop to get rid of the fixed 100ms delay.
Now collecting 15k samples/second.
Change-Id: Iba5e73e96e8d226a0b5777ecac19453c152dc634
* Fix build.
Change-Id: If2fe7a0c77e0d6545c93fa0d4a013c50a9b9d896
* Fix the mess I left after resolving conflicts.
Change-Id: I96abd47a7834bf8f5e005ba63020f0a0cc429548
* Support 64-bit address in memory sampling.
* Support sampling 64-bit values.
* Better error reporting. WIP on 64-bit support.
* Speed up single 32-bit memory sample.
21k samples/second.
* WIP on review feedback.
Change-Id: I00e453fd685d173b0206d925090beb06c1f057ca
* Make memory sample buffers/config per-target.
Change-Id: I5c2f5997795c7a434e71b36ca4c712623daf993c
* Document, and add bucket clear option.
Change-Id: I922b883adfa787fb4f5a894db872d04fda126cbd
Signed-off-by: Tim Newsome <tim@sifive.com>
* Fix whitespace.
Change-Id: Iabfeb0068d7138d9b252ac127d1b1f949cf19632
Signed-off-by: Tim Newsome <tim@sifive.com>
* Document sample buffer full behavior.
Change-Id: Ib3c30d34b1f9f30cf403afda8fdccb850bc8b4df
Signed-off-by: Tim Newsome <tim@sifive.com>
* Actually clear the sample buffer in dump_sample_buf.
Change-Id: Ifda22643f1e58f69a6382abc90474659d7330ac5
Signed-off-by: Tim Newsome <tim@sifive.com>
* Use compatible string formatting.
Change-Id: Ia5e5333e036c1dbe457bc977fcee41983b9a9b77
Signed-off-by: Tim Newsome <tim@sifive.com>
* Improve riscv expose_[csrs|custom] commands
* Add option to specify custom name for registers.
* Allow to call commands multiple times without loss of previous data.
* Make sure the commands can only be used in the config phase (before "init").
* Validity checks and warnings.
* Change commands to be per target.
* Fix memory leaks.
* Also fix unrelated memory leaks to keep valgrind happy.
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* fixes after review
* improve error message
* Allocate RISC-V arch_info during target creation
* Ensured that target->arch_info is allocated as soon as the
target is created. Needed so that per-target config commands
(e.g. "riscv set_mem_access") can be executed also in the
OpenOCD's config phase (before calling "init").
* Added several assert()'s for safety.
Signed-off-by: Jan Matyas <matyas@codasip.com>
* Removed a TODO comment
* Add flexible selection of memory access methods, detection of aampostincrement.
New configuration command introduced: "riscv set_mem_access".
It allows to specify which RISC-V memory access methods (progbuf,
sysbus and/or abstract access) should be tried and in which order
of priority.
Command "riscv set_prefer_sba" is left and works in backward
compatible way, but is marked as deprecated.
First time abstract memory access is executed, it is tried with
set aampostincrement bit. If the abstract command fails or the
address is not incremented correctly, aampostincrement will not
be used for any subsequent accesses.
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* remove unnecessary variable
* fix doc
* WIP, apply stash with conflicts.
Change-Id: Ia794bde419aa29161c68898d20e30527e69f5a31
* Fix conflict resolution problems.
Change-Id: I4cedc348cf613f98cc5a36886f37c568ca644238
* Add repeat_read command.
Only implemented for sba v1 right now, and poorly tested at that.
Change-Id: I1d9ff63e1dea14b3f6a9f8ba4dad53668bf8038b
* Hide bogus address in repeat_read
Change-Id: Ib66c1fa60df9c7fc7cc87880b0fddc52825b48aa
* WIP make repeat read work with progbuf.
Change-Id: I555f8b880c8bf0d1ed0f3f90c7987a5b516a7a79
* WIP
Change-Id: Ic567cea68355ae907e94bd25185a2c9be6fd798d
* Fix error handling when increment is non-zero.
Change-Id: I5a2f3f2ee948fd4e12c0443a542e85b7b5c5791a
* Correctly(?) handle failures when increment is 0.
I'm not 100% convinced that this ensures every read value shows up in
the output, but it ought to work.
Change-Id: I1af3e7174cf9d5e6f293456fb5ead629e17faaaa
* Don't crash when asked to read no data.
Change-Id: I4061b5c720a43a4f828384ab9eacc89557adfa05
* Remove unnecessary comment.
Change-Id: I1be3d699b86299339b3a830ca1ef13c9f5b9fe0f
* Document `riscv repeat_read`.
Change-Id: I4a0f071f38784b2de034f8c1b0ce75d6d2d326b2
Issue identified by checkpatch script from Linux kernel v5.1 using
the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types FUNCTION_ARGUMENTS -f {} \;
This patch also fixes an incorrect function prototype in zy1000.c.
ZY1000 minidriver implementation overrides the function
arm11_run_instr_data_to_core_noack_inner(), but the prototype is
not the same as in src/target/arm11_dbgtap.c and to avoid compile
error it was changed also the prototype of the called function
arm11_run_instr_data_to_core_noack_inner_default().
Change-Id: I476cda8cdb0e1e280795b3b43ca95c40d09e4a3d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5630
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
* Accommodate users setting custom triggers.
RISC-V hardware supports many more triggers than gdb can communicate to
OpenOCD. Accommodate users that set triggers by writing tdata* directly,
by disable/step/reenable when a user has done that.
Note that users must set dmode in tdata1 for this behavior to work
properly. Triggers with dmode=0 are assumed to be set and handled by the
software that is being debugged.
Change-Id: Ib0751689c5553aae3a273395b10f5b98326fa066
* Enumerate triggers when resuming from a trigger
Otherwise when we connect to a target that's already halted due to a
trigger, we won't correctly step past it.
Change-Id: I23b9482fa9597af826770f9cebf247b7ba59f65c
* Also disable/reenable triggers around single step.
Gdb is smart enough to disable/step/resume if it set the triggers, but
if a user set them manually it also needs to happen.
Change-Id: I1251bd47199b6f15f61a93e3a521a53f2b677c5f
* Fix whitespace.
Change-Id: Icc240aecbc7e3e36ce4e4d784f5703304334ca13
* WIP making semihosting work with -rtos hwthread.
Change-Id: Icb46f3eeedc1391e8fdc73c3ad8036f20267eb2e
* More WIP.
Change-Id: I670a6e1ba2a13a6ef2ae303a99559a16fdd1bbfb
* Fix halting due to a trigger.
Change-Id: Ie7caa8dde9518bcd5440e34cf31ed0d30ebf29ad
* Fix multicore semihosting without halt groups.
Change-Id: I53587e5234308ed2cc30a7132c86e4c94eb176c4
* WIP
Change-Id: I40630543b08d8b533726cb3f63aa60a62be8ef40
* Fix single core semihosting.
This was the last bug!
Change-Id: I593abac027fa9707f48b7f58163d7089574a0e28
* Fix whitespace.
Change-Id: I285c152970b87864c63803fae61312e5b79dfe6d
* Cache accesses through riscv_[sg]et_register.
This helps a lot with the address translation code, which checks satp
over and over again. Now satp is only read once per halt. It should also
help in a few other cases (but I don't have a good test setup to really
measure the impact).
Change-Id: I90392cc60d2145a70cf6c003d6a956dc9f3c0cc4
* Fix whitespace.
Change-Id: I05c5342d8a461cd8c618a3f60296925e9e84643f
* Don't read registers that we know don't exist.
Change-Id: Ie5c6226b3d4ecb6cf8f0d8954a52fda88e6e5bdd
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.
Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
* WIP
Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd
* Reading v* registers appears to work.
Can't really test it though, because gdb doesn't print them right.
Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5
* Total hack to communicate registers to gdb.
Change-Id: Id06c819675f2a5bcaf751e322d95a7d71c633765
* Implement writing vector registers.
Fixed reading vector registers.
Change-Id: I8f06aa5ee5020b3213a4f68644c205c9d6b9d214
* Show gdb the actual size of the vector registers.
This length may be different per hart.
Change-Id: I92e95383da82ee7a5c995822a53d51b1ea933493
* Remove outdated todo comment.
Change-Id: Ic9158b002858f0d15a6452773b095aa5f4501128
* Removed TODO comment.
Filed #449 to track this.
Change-Id: I5277b19e545df2024f34cda39158ddf7d0d89d47
* Nicely handle some errors reading/writing V regs.
Change-Id: Ia7bb63a5f9433d9f7b46496b2c0994864cfc4a09
Fix memory access on 64-bit targets with no progbuf and sba that
supports 32-bit accesses but not 64-bit accesses. Bug was introduced in #419.
This fixes https://github.com/riscv/riscv-tests/issues/217.
Change-Id: Ib5ddf9886b77e3d58fe1d891b560ad03d5a46da1
* fix for batch scans not honoring presence of BSCAN tunnel
* fix formatting to placate checkpatch
* replace DIM with ARRAY_SIZE
* Refactor code that adds a bscan tunneled scan.
* Move bscan tunnel context to the batch structure, and in array
form, one per scan
* adjust code that was inconsistent with project code formatting standards
* 64-bit progbuf memory reads work.
Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399
* 64-bit writes work.
Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23
* Let targets indicate number of supported data bits.
This is used by the default memory read/write functions when creating an
aligned block.
I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.
Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b
* Make mingw32 happy.
Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
Tim Newsome
Jan Matyas
Dolu1990
Erhan Kurubas
Jan Matyas
Antonio Borneo
Samuel Obuch
Hsiangkai
bluew
Greg Savin