Commit Graph

11736 Commits

Author SHA1 Message Date
Tim Newsome 70668f5ec5
Merge pull request #959 from en-sc/en-sc/progbuf-mem-write
target/riscv: improve error handling in `write_memory_progbuf()`
2023-12-11 09:22:55 -08:00
Tim Newsome b5e0ec3c97
Merge pull request #973 from kr-sc/kr-sc/update-debug-defines-os
Update riscv/debug_defines (to sync with riscv-debug-spec commit 40b9a05)
2023-12-11 09:05:42 -08:00
Kirill Radkin 84e6a4e617 Update riscv/debug_defines (to sync with riscv-debug-spec:40b9a05)
Change-Id: Ie969866d1de83360a5f45e96e22108b58b8aa02f
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-12-07 20:59:10 +03:00
Evgeniy Naydanov 8584b14183 target/riscv: improve error handling in `write_memory_progbuf()`
The goal of this commit is to provide more robust error handling in
`write_memory_progbuf()`. This is achieved by rewriting it in a fashion
similar to `read_memory_progbuf()`.

The motivation is: some instability in `load_image` was encountered. No
stable reproduction could be obtained, so the root cause was not
determined. Therefore, it was decided to clean-up the code, that may be
implicated in such failures.

Examples of unhanded errors in the code prior to this commit:
* Most of `dmi_write()` return values are discarded.
* If `dm_read()` on `abstractcs` failed (line 4546), `abstractauto` was
  not cleared.

Furthermore, the structure of the code was quite complicated, which made
it hard to analyze and reason whether or not all possible failures are
handled properly.

Change-Id: I8a100b686e594855fbf34acf5ccf0e1550f18869
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-12-07 12:57:05 +03:00
Tim Newsome 7c94814221
Merge pull request #972 from en-sc/en-sc/decode-location
target/riscv: report helpfull location during register decode
2023-12-06 15:59:44 -08:00
Evgeniy Naydanov 560c338526 target/riscv: avoid using VLA in `log_debug_reg()`
OpenOCD style guide(`doc/manual/style.txt`) prohibits use of VLA:

> - use malloc() to create dynamic arrays. Do @b not use @c alloca
> or variable length arrays on the stack. non-MMU hosts(uClinux) and
> pthreads require modest and predictable stack usage.

Change-Id: I12e4a5087fd056d69866137237af6deca27f5d33
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-12-01 16:45:48 +03:00
Evgeniy Naydanov f5b8862a76 target/riscv: report helpfull location during register decode
`LOG_TARGET_DEBUG()` reports file, line and function name at the call
site. This information is not helpfull if it always points to the same
location inside `log_debug_reg()`.

Change-Id: Ib73be0344fb5c80c9ac8e5fdee1084d405522eb7
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-12-01 16:45:30 +03:00
Tim Newsome d4c5d26570
Merge pull request #969 from aap-sc/aap-sc/final_november_2023_upstream_sync_fixup
fix erroneously-resolved merge conflict
2023-11-30 12:18:33 -08:00
Parshintsev Anatoly 10af616067 fix erroneously-resolved merge conflict
Change-Id: I4278e3e444eec93c418dfe153f60404f9848a20a
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-11-29 20:51:42 +03:00
Tim Newsome e9484bab54
Merge pull request #967 from riscv/from_upstream
Merge up to 4b1ea8511a from upstream
2023-11-29 09:24:27 -08:00
Kirill Radkin c5185e9219 breakpoints: Fix endless loop in bp/wp_clear_target
If we can't remove bp/wp, we will stuck in endless loop

Change-Id: I44c0a164db1d15c0a0637d33c75087a49cf5c0f4
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7940
Tested-by: jenkins
Reviewed-by: Anatoly P <kupokupokupopo@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-11-27 10:09:35 -08:00
Tim Newsome 84bcf9aa8b Merge commit '4b1ea8511a7da9d7201df40302e3341c6e97ffdd' into from_upstream
Change-Id: I59366e08a4ac7e443e426b5fd6727c649f1ac9d5
2023-11-27 10:04:09 -08:00
Tim Newsome 0deaa63f50 Merge commit '022e438292de992cc558f268b2679e76ad313db6' into from_upstream
There was a big conflict with this one incoming change. This version of
the code passes all the tests (which don't test for the changed behavior
at all AFAIK), and at least passes errors back everywhere.

Conflicts:
	src/target/breakpoints.c

Change-Id: I72f75a3e08deda7e624e8bb82e1a9ea07a7a9276
2023-11-27 10:03:56 -08:00
Tim Newsome 92213132a6 Merge commit '18281b0c497694d91c5608be54583172838be75c' into from_upstream
Change-Id: I05cd5ef9b04fa61a27321ae9b6a4fecabe3dee80
2023-11-20 12:30:19 -08:00
Tim Newsome af786c0eca
Merge pull request #963 from kr-sc/kr-sc/no-free-triggers
When an attempt to set watchpoint fails because there is no free triggers OpenOCD reports "unknown error"
2023-11-17 09:18:44 -08:00
Tim Newsome 334f690f2a
Merge pull request #958 from riscv/set_field_get_field
target/riscv: Replace [sg]et_field macros with functions.
2023-11-16 15:22:57 -08:00
Tim Newsome d5ea55cfca
Merge pull request #957 from riscv/sbbusyerror
target/riscv: Handle sbbusyerror in read_memory_bus_v1
2023-11-16 09:39:41 -08:00
Tim Newsome 46e8f7a566
Merge pull request #951 from en-sc/en-sc/scan-dump-reg
target/riscv: dump_field() shouldn't always decode
2023-11-16 09:20:33 -08:00
Kirill Radkin fee2e04d90 When an attempt to set watchpoint fails because there is no free triggers OpenOCD reports "unknown error"
Now it returns `resource not available`

Change-Id: Ifbbd468bdf62023850690eb96fe8a16f4114e915
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-11-16 17:18:22 +03:00
Tim Newsome 08182bfc6b target/riscv: Handle sbbusyerror in read_memory_bus_v1
The existing code didn't seem to work right at all. I have spike
modifications that exercise these new cases. I'll merge those once this
has merged.

Change-Id: I89bd336f34f1b208a76f25b6b41fe3877800765b
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-11-15 11:27:32 -08:00
Tim Newsome 86b430b6b4 target/riscv: Replace [sg]et_field macros with functions.
Compilers are good at optimizing, and with functions it's abundantly
clear what all the types involved are. This change means we don't have
to be super careful about the type of values because of what the macro
might do to them that might cause overflow.

The only place where the return type matters is in printf-style
functions, and I made get_value32() for those cases where a change was
needed.

This should set the stage for simply copying the latest debug_defines.h
from the debug spec build again.

Change-Id: I5fb19d0cfc1e20137832a7b344b05db215ce00e1
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-11-15 11:12:09 -08:00
Evgeniy Naydanov 00320fd198 target/riscv: replace `__PRETTY_FUNCTION__` with `__func__`
The reasoning for the change:
* `__func__` is part of C99, `__PRETTY_FUNCTION__` is GNU extension.
* `__PRETTY_FUNCTION__` is defined to be the same as `__func__` for C
  sources by GCC documentation but differ for C++ sources (full
  signature instead of just a name).
* Currently Clang does support `__PRETTY_FUNCTION__`, though it uses
  GCC's C++ variant across C and C++.

Therefore using `__PRETTY_FUNCTION__` creates confusion and does not
provide any valueble information in the logs.

Change-Id: Ie0db6d73f602784b6752a30911dcef3dd7ee4594
2023-11-15 14:06:29 +03:00
Evgeniy Naydanov 3b0c654c67 target/riscv: dump_field() shouldn't always decode
Sometimes, the value from of some DMI scans has no meaning (e.g. when
`op` is read). Such values should not be decoded. To make the dumps more
consistent, `<no decoding available>` is printed when there is no
decoding for a register.

Change-Id: I415f06a5a80f2fc8fb8ab3f79132bdf0602c8ad6
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-11-15 14:06:29 +03:00
Tim Newsome 6de536bbb8
Merge pull request #961 from en-sc/en-sc/coreid-target-riscv
target/riscv: clarify usage of `coreid`
2023-11-13 09:45:58 -08:00
Tim Newsome 1ea0e9b426
Merge pull request #928 from AnastasiyaChernikova/triggers
target/riscv: cache requests to trigger configuration
2023-11-10 12:12:03 -08:00
Evgeniy Naydanov 5ec9938c61 target/riscv: clarify usage of `coreid`
By definition in `target/target.h`, `coreid` is not a unique identifier
of a target -- it can be the same for targets on different TAPs.

Change-Id: Ifce78da55fffe28dd8b6b06ecae7d8c4e305c0a2
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-11-10 13:11:12 +03:00
Tim Newsome 6f028846a4
Merge pull request #955 from MarekVCodasip/use-watchpoint-mask-macro
target/riscv: Replace watchpoint value mask comparison value with macro.
2023-11-09 08:54:47 -08:00
Marek Vrbka 2357237815 target/riscv: Replace watchpoint value mask comparison value with macro.
This patch replaces ~(typeof(watchpoint->mask))0 with
WATCHPOINT_IGNORE_DATA_VALUE_MASK. This improves
readability and moves the RISCV target in line with
other targets.

Change-Id: I15ac4d4ee76098b304d9b22f720911ba4329c190
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-11-09 10:11:22 +01:00
Tim Newsome f119c1d480
Merge pull request #954 from riscv/from_upstream
Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' from upstream
2023-11-07 09:17:37 -08:00
Tim Newsome 5653f512a2
Merge pull request #952 from MarekVCodasip/stop-caching-dpc
target/riscv: Stop caching writes to DPC
2023-11-07 09:04:58 -08:00
Anastasiya Chernikova fea20e2bf5 target/riscv: cache requests to trigger configuration
Depending on configuration, the existing implementation of watchpoints is
rather inefficient for certain scenarios. Consider HW that:

1. triggers 0-3 can be used as instruction breakpoints
2. triggers 4-7 can be used as data breakpoints (watchpoints)
3.  NAPOT triggers are not supported.

Now, consider that we have a pending watchpoint. And we perform a "step"
operation. According to the current implementation:

* OpenOCD will disable watchpoints
* Perform a single-step
* Will try to restore the original watchpoints. It will need 12 attempts
to find a suitable trigger: (8 attempts to try NAPOT, and another 4 to try
GE+LE).

This patch introduces a dedicated cache for requests to triggers. It
significantly speeds things up, since we cache failed attempts and no
additional interactions with HW is necessary.

Change-Id: Ic272895eaa763a7ae84d14f7633790afd015ca9d
Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2023-11-07 14:51:49 +03:00
Tim Newsome b5bd88441c Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' into from_upstream
Conflicts:
	src/jtag/drivers/xds110.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg

Change-Id: If0c02817df03b7fd700cc84b4da2c02d36737d28
2023-11-06 09:25:46 -08:00
Tim Newsome 839f292f83
Merge pull request #953 from riscv/regno_name_enum
target/riscv: gdb_regno_name takes an enum.
2023-11-06 09:16:57 -08:00
Tim Newsome c2f544c4f6 target/riscv: gdb_regno_name takes an enum.
Otherwise it won't compile for me. Not sure why that doesn't affect the
automated builds.

Change-Id: Ic66c743e1698c4c0772e5601723cb5c711b4fa5c
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-11-03 10:48:05 -07:00
Tim Newsome b75bfab026
Merge pull request #896 from AnastasiyaChernikova/ac-sc2
target/riscv: Adding register tables to make register names consiste
2023-11-03 10:30:35 -07:00
Tim Newsome 2676f05f2f
Merge pull request #947 from riscv/from_upstream
From upstream
2023-11-03 10:13:05 -07:00
Marek Vrbka adb9c3209e target/riscv: Stop caching writes to DPC
Since DPC is WARL (same rules as MEPC according to
the specification), it is possible that
writes to it won't result in the exact value present.
Therefore, writes to it shouldn't be cached, same as
with other WARL registers.

Change-Id: I818c0cef9727b999b7d84b19f9f42cd706c99d69
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-11-03 12:11:01 +01:00
Tim Newsome 20bcd83bca
Merge pull request #945 from kr-sc/kr-sc/fix-mmu-access-upstream
target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
2023-11-02 09:33:55 -07:00
Anastasiya Chernikova 805d394ff8 target/riscv: Adding register tables to make register names consistent
Added the ability to enter dimensionless registers

Change-Id: I1b781959ce4690ec65304142bd9a7c6f540b3e86
Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2023-11-02 17:21:59 +03:00
Tim Newsome dc782f6d94
Merge pull request #949 from riscv/remove_esp32c_targets_from_doc
Remove mention of esp32c2, esp32c3 from doc
2023-11-01 09:07:59 -07:00
Tim Newsome 585f5db11c
Merge pull request #950 from riscv/remove_set_scratch_ram_from_doc
Remove mention of "riscv set_scratch_ram" from doc
2023-10-31 09:55:06 -07:00
Tim Newsome 51679e3e6b
Merge pull request #948 from riscv/uninitialized_dump
target/riscv: Prevent dump_field() reading uninitialized memory
2023-10-31 09:48:17 -07:00
Jan Matyas c127e84563 Removed mention of "riscv set_scratch_ram" from doc
This command no longer exists, was removed in:
ead2a595b8

Remove it from the doc as well.

Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-31 17:01:18 +01:00
Jan Matyas 2d9c7a7a77 Remove mention of esp32c2, esp32c3 from doc
Targets "esp32c2" and "esp32c3" should not be mentioned in the doc
under "target types" because these are not standalone OpenOCD
targets.

They are merely a set of .cfg files which use the generic
"riscv" target.

Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-31 16:52:02 +01:00
Tim Newsome e474d1d54a target/riscv: Prevent dump_field() reading uninitialized memory
Change-Id: I9ef8f2c2e9a824aa6595e8f20682c968ae5aed72
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-30 09:21:19 -07:00
Tim Newsome c92149afc3
Merge pull request #943 from riscv/remove_deprecated_gd32vf103_flash
Removed deprecated gd32vf103_flash
2023-10-30 08:44:31 -07:00
Kirill Radkin 57c3f0d91c target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
Now:
1) If mmu is disabled, virt2phys succeeded and returns physical address
2) If mmu is enbaled, but translation fails, read/write_memory fails

Change-Id: I312309c660239014b3278cb77cadc5618de8e4de
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-30 15:59:41 +03:00
Jan Matyas d14b71cd36 Removed deprecated gd32vf103_flash
Removing flash driver "gd32vf103_flash".

This driver has been deprecated since June-1-2022, and was scheduled
for removal in June 2023.

Change-Id: Ib6f4dcba11e91a095b3a20eedd864589084b7fa9
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-30 07:20:35 +01:00
Tim Newsome f02fe0960c Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstream
Conflicts:
	HACKING
	src/target/riscv/riscv-013.c

Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
2023-10-27 09:00:59 -07:00
Tim Newsome 89260a5f1f
Merge pull request #942 from riscv/from_upstream
From upstream
2023-10-27 08:46:43 -07:00