interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Remove mention of esp32c2, esp32c3 from doc 

Targets "esp32c2" and "esp32c3" should not be mentioned in the doc
under "target types" because these are not standalone OpenOCD
targets.

They are merely a set of .cfg files which use the generic
"riscv" target.

Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
This commit is contained in:
Jan Matyas 2023-10-31 16:52:02 +01:00
parent c92149afc3
commit 2d9c7a7a77
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
doc/openocd.texi
View File

@ -4838,8 +4838,6 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
@item @code{esirisc} -- this is an EnSilica eSi-RISC core.
The current implementation supports eSi-32xx cores.
@item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
@item @code{esp32c2} -- this is an Espressif SoC with single RISC-V core.
@item @code{esp32c3} -- this is an Espressif SoC with single RISC-V core.
@item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
@item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores.
@item @code{fa526} -- resembles arm920 (w/o Thumb).