From 2d9c7a7a771cd64d63342bc0a6e3d520dc693bfe Mon Sep 17 00:00:00 2001 From: Jan Matyas Date: Tue, 31 Oct 2023 16:52:02 +0100 Subject: [PATCH] Remove mention of esp32c2, esp32c3 from doc Targets "esp32c2" and "esp32c3" should not be mentioned in the doc under "target types" because these are not standalone OpenOCD targets. They are merely a set of .cfg files which use the generic "riscv" target. Signed-off-by: Jan Matyas --- doc/openocd.texi | 2 -- 1 file changed, 2 deletions(-) diff --git a/doc/openocd.texi b/doc/openocd.texi index 7e9eb2036..afd853615 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4838,8 +4838,6 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores @item @code{esirisc} -- this is an EnSilica eSi-RISC core. The current implementation supports eSi-32xx cores. @item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores. -@item @code{esp32c2} -- this is an Espressif SoC with single RISC-V core. -@item @code{esp32c3} -- this is an Espressif SoC with single RISC-V core. @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core. @item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores. @item @code{fa526} -- resembles arm920 (w/o Thumb).