Commit Graph

9243 Commits

Author SHA1 Message Date
Marek Vrbka 2357237815 target/riscv: Replace watchpoint value mask comparison value with macro.
This patch replaces ~(typeof(watchpoint->mask))0 with
WATCHPOINT_IGNORE_DATA_VALUE_MASK. This improves
readability and moves the RISCV target in line with
other targets.

Change-Id: I15ac4d4ee76098b304d9b22f720911ba4329c190
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-11-09 10:11:22 +01:00
Tim Newsome f119c1d480
Merge pull request #954 from riscv/from_upstream
Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' from upstream
2023-11-07 09:17:37 -08:00
Tim Newsome 5653f512a2
Merge pull request #952 from MarekVCodasip/stop-caching-dpc
target/riscv: Stop caching writes to DPC
2023-11-07 09:04:58 -08:00
Tim Newsome b5bd88441c Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' into from_upstream
Conflicts:
	src/jtag/drivers/xds110.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg

Change-Id: If0c02817df03b7fd700cc84b4da2c02d36737d28
2023-11-06 09:25:46 -08:00
Tim Newsome c2f544c4f6 target/riscv: gdb_regno_name takes an enum.
Otherwise it won't compile for me. Not sure why that doesn't affect the
automated builds.

Change-Id: Ic66c743e1698c4c0772e5601723cb5c711b4fa5c
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-11-03 10:48:05 -07:00
Tim Newsome b75bfab026
Merge pull request #896 from AnastasiyaChernikova/ac-sc2
target/riscv: Adding register tables to make register names consiste
2023-11-03 10:30:35 -07:00
Tim Newsome 2676f05f2f
Merge pull request #947 from riscv/from_upstream
From upstream
2023-11-03 10:13:05 -07:00
Marek Vrbka adb9c3209e target/riscv: Stop caching writes to DPC
Since DPC is WARL (same rules as MEPC according to
the specification), it is possible that
writes to it won't result in the exact value present.
Therefore, writes to it shouldn't be cached, same as
with other WARL registers.

Change-Id: I818c0cef9727b999b7d84b19f9f42cd706c99d69
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-11-03 12:11:01 +01:00
Tim Newsome 20bcd83bca
Merge pull request #945 from kr-sc/kr-sc/fix-mmu-access-upstream
target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
2023-11-02 09:33:55 -07:00
Anastasiya Chernikova 805d394ff8 target/riscv: Adding register tables to make register names consistent
Added the ability to enter dimensionless registers

Change-Id: I1b781959ce4690ec65304142bd9a7c6f540b3e86
Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2023-11-02 17:21:59 +03:00
Tim Newsome 51679e3e6b
Merge pull request #948 from riscv/uninitialized_dump
target/riscv: Prevent dump_field() reading uninitialized memory
2023-10-31 09:48:17 -07:00
Tim Newsome e474d1d54a target/riscv: Prevent dump_field() reading uninitialized memory
Change-Id: I9ef8f2c2e9a824aa6595e8f20682c968ae5aed72
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-30 09:21:19 -07:00
Kirill Radkin 57c3f0d91c target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
Now:
1) If mmu is disabled, virt2phys succeeded and returns physical address
2) If mmu is enbaled, but translation fails, read/write_memory fails

Change-Id: I312309c660239014b3278cb77cadc5618de8e4de
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-30 15:59:41 +03:00
Jan Matyas d14b71cd36 Removed deprecated gd32vf103_flash
Removing flash driver "gd32vf103_flash".

This driver has been deprecated since June-1-2022, and was scheduled
for removal in June 2023.

Change-Id: Ib6f4dcba11e91a095b3a20eedd864589084b7fa9
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-30 07:20:35 +01:00
Tim Newsome f02fe0960c Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstream
Conflicts:
	HACKING
	src/target/riscv/riscv-013.c

Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
2023-10-27 09:00:59 -07:00
Tim Newsome 89260a5f1f
Merge pull request #942 from riscv/from_upstream
From upstream
2023-10-27 08:46:43 -07:00
Tim Newsome b48636158a
Merge pull request #944 from riscv/remove_extra_kept_alive
Remove an extra call to kept_alive()
2023-10-26 09:18:47 -07:00
Evgeniy Naydanov 57b67eda38 target/riscv: update debug register printers
Change-Id: I069bbe069a3aaa7fd3a4f6eccde40f813db33cc9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-10-25 19:16:36 +03:00
Jan Matyas a26c90f220 Remove an extra call to kept_alive()
This incorrect extra call has been removed in upstream code already
in March 2022, see https://review.openocd.org/c/openocd/+/6836 .

Remove it from riscv-openocd as well.

Change-Id: Ie341f5578c8bfdc518adf1e4bc134919ab76f803
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-25 12:44:01 +02:00
Tim Newsome 2d98ef5d13
Merge pull request #941 from kr-sc/kr-sc/fix-hgatp-mode-upstream
hgatp_mode in riscv_virt2phys_v defined by vsatp value
2023-10-24 07:57:37 -07:00
Tim Newsome 03fff0f86c Fix build.
Change-Id: I20bd0356c63745423e23aec71f272fe2e32db88e
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-23 12:35:45 -07:00
Tim Newsome af08d582b5 Merge commit 'e17fe4db0f256ee4fb97dcfd6b9f7f55c966b190' into from_upstream
Conflicts:
	src/flash/nor/drivers.c
	src/target/riscv/riscv.c

Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd
2023-10-23 12:29:21 -07:00
Tim Newsome 132e3faf1d
Merge pull request #940 from riscv/revert-908-disable-soft-bp-size-2-non-compressed
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported"
2023-10-23 11:45:50 -07:00
Kirill Radkin 109772012a hgatp_mode in riscv_virt2phys_v defined by vsatp value
Replace `vsatp` with `hgatp` (how it should be)

Change-Id: Ie548467b06d1fb266ccc56cbec1aff8d9f435973
2023-10-23 18:56:40 +03:00
Tim Newsome 3b0561d081
Merge pull request #935 from riscv/from_upstream
Merge down up to 0384fe5 from upstream.
2023-10-23 08:38:48 -07:00
Tim Newsome 912de786a4
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported" 2023-10-20 15:37:28 -07:00
Tim Newsome 2f71800cbb flash/stm32lx: Revert to upstream version.
Reintroduce checkpatch problem, because now we can handle them better.

Change-Id: Ib81b9910433ae1a240630b898edb19da8d2d5d83
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-17 14:22:17 -07:00
Tim Newsome a495dd854c
Merge pull request #934 from kr-sc/kr-sc/revert-commit
Revert "target: Update messages connected with `examine`"
2023-10-17 09:46:31 -07:00
Kirill Radkin 6c96b9d8c3 Revert "target: Update messages connected with `examine`"
This reverts commit a3db93b1ce.

Reason for revert: https://github.com/riscv/riscv-openocd/pull/931#issuecomment-1761550506
2023-10-17 12:57:39 +03:00
Tim Newsome 53fcf14d83 Merge commit '0384fe5d596f42388f8b84d42959d899f29388ab' into from_upstream
Conflicts:
      .github/workflows/snapshot.yml
      src/rtos/FreeRTOS.c

Change-Id: I4c9ff887b69140e0f61cb3f75a2f2c1a12071320
2023-10-16 12:30:06 -07:00
Tim Newsome e1fa78d1b3
Merge pull request #929 from aap-sc/riscv
do not assume DTM version unless dtmcontrol is read successfully
2023-10-16 12:10:25 -07:00
Tim Newsome d454854c13 server/gdb_server: Fake resuming unavailable targets.
When asked to resume an unavailable target, resume any available targets
and report success.

Change-Id: Ieafc63794c1a6eba8948c0f9ce84fa74f9765041
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-13 08:32:19 -07:00
Tim Newsome 6e9514efcd
Merge pull request #926 from riscv/unavailable_events
server/gdb_server: Handle events if first target is unavailable
2023-10-11 13:00:21 -07:00
Tim Newsome 6f4b90afb7
Merge pull request #925 from riscv/unavailable_reg
gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not imple…
2023-10-11 13:00:03 -07:00
Tim Newsome beb705912b
Merge pull request #917 from kr-sc/kr-sc/disable-triggers-option
provide riscv-specific controls to disable triggers from being used for watchpoints
2023-10-11 12:34:07 -07:00
Tim Newsome 41d1ee3715
Merge pull request #931 from kr-sc/kr-sc/update-examine-messages
target: Update messages connected with `examine`
2023-10-11 12:33:38 -07:00
Tim Newsome 52c9ae0aa1 server/gdb_server: Handle events if first target is unavailable
When a target in an SMP group is unavailable, the gdb layer might get an
event for a different target in that SMP group, but not one that is the
primary target for that gdb connection. So propagate events if they're
for any of the targets in the SMP group, not just if it's for the first
one in that group.

Change-Id: I8d6738762acc7c0aef96f56ce2cb7f2eeb233b33
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-10 10:57:30 -07:00
Tim Newsome 969b30326c rtos: Refactor rtos_get_gdb_reg()
Exit early if conditions aren't satisfied, instead of putting the core
code inside an if().

Also return ERROR_FAIL if conditions are satisfied but no matching
registers were found.

Change-Id: I77aa63d9f707bc38d1a71899275ba603914b52c9
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-10 10:51:47 -07:00
liangzhen 3f1339f8e8 target/riscv: use cacheable read/write function to handle DCSR
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-07 09:26:31 +08:00
Parshintsev Anatoly 2c4118ecea do not assume DTM version unless dtmcontrol is read successfully
Change-Id: I5f2003b7ac5ce87af6ca9a4fcb46140682a8cfdf
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-10-06 18:51:53 +03:00
Tim Newsome 28f630d245
Merge pull request #924 from riscv/unavailable_step
server/gdb_server: Step unavailable targets.
2023-10-05 12:12:16 -07:00
Tim Newsome 599e0a22e8
Merge pull request #915 from riscv/dpc_print
target/riscv: Remove duplicate read PC message
2023-10-05 12:05:16 -07:00
Kirill Radkin a3db93b1ce target: Update messages connected with `examine`
Move `examine_attempted` flag to target struct to make it target specific.
`Info` messages for retry and `Error` messages for failure added.

Change-Id: Id2fbe7dc68d746c936c8412289d0d149fbd80d71
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-03 16:28:28 +03:00
Kirill Radkin e76a9b799d provide riscv-specific controls to disable triggers from beeing used for watchpoints
Add a new riscv specific commands to disable triggers

Change-Id: Ic1842085aa66851c740e0abcbfbe0adbe930920e
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-02 11:54:07 +03:00
Tim Newsome 2f1714789b
Merge pull request #921 from lz-bro/repeat_read-fix
target/riscv: support riscv repeat_read by sysbus access
2023-09-29 09:31:59 -07:00
Tim Newsome 75b5de67df
Merge pull request #918 from kr-sc/kr-sc/allow-to-query-status-dcsr-ebreak
openocd does not allow to query status of dcsr.ebreak{u,s,m}
2023-09-29 09:30:46 -07:00
Tim Newsome ef3be96ba1
Merge pull request #892 from en-sc/en-sc/register-printing
target/riscv: define register printers
2023-09-28 08:36:36 -07:00
Tim Newsome 15f399691e gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not implemented
If it fails, then pass that failure on. If it's simply not implemented,
then we can fall through and try target_get_gdb_reg_list_noread().

This difference matters when the target representing the current
hwthread is unavailable, but the target that is linked to the gdb
connection is available. In that case we want the operation to return an
error to gdb, instead of reading the register from the target that is
available.

Change-Id: I9c84ca556f818c5580e25ab349a34a226fcf0f43
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-27 13:52:11 -07:00
Tim Newsome 944fe66f10 server/gdb_server: Step unavailable targets.
When gdb requests to step an unavailable target, report success. When
the target becomes available, the step can complete.

Change-Id: I969ab56139f72a757552928d59edf6eabd598fa4
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-27 13:08:50 -07:00
Kirill Radkin ee2bc807eb openocd does not allow to query status of dcsr.ebreak{u,s,m}
Extend riscv set_ebreak* commands.
Now it can be called without args to print current value.

riscv_ebreak* flags are moved to riscv_info struct.

Change-Id: Ib46e6b6dfc0117599c7f6715c7aaf113e63bd7dc
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-09-26 11:52:30 +03:00