Commit Graph

6213 Commits

Author SHA1 Message Date
Megan Wachs 6e16ef2bd4 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-08-15 17:22:48 -07:00
Megan Wachs 6200d9a180 Merge branch 'riscv_timeout_commands' into riscv-compliance 2017-08-15 17:22:08 -07:00
Megan Wachs 94de39c221 riscv: Put commandd_handlers before they are needed. Tabs vs spaces. 2017-08-15 17:04:59 -07:00
Megan Wachs 879c274cb9 riscv: Add commands for setting timeouts 2017-08-15 15:59:40 -07:00
Megan Wachs 3ec1772c96 riscv: Add commands for setting timeouts 2017-08-15 15:55:09 -07:00
Tim Newsome 5c39079a62 Remove some unnecessary casts. 2017-08-15 14:29:24 -07:00
Megan Wachs 25eedb94a5 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-08-14 12:08:58 -07:00
Tim Newsome 2706df0ec3 Fix a corner case in block memory read. 2017-08-13 14:14:23 -07:00
Gleb Gagarin 3109da7dfd Force actual read from prog buffer for the last transaction in read_memory() 2017-08-12 14:51:12 -07:00
Gleb Gagarin e676d3dae6 Fixed off-by-one error in previous commit 2017-08-11 17:46:35 -07:00
Gleb Gagarin 39b01259fa fixed memory leak introduced by previous commit 2017-08-10 16:37:50 -07:00
Gleb Gagarin b5692585de Fix reads beyond requested memory range 2017-08-10 14:27:11 -07:00
Tim Newsome efcfcf555f Fix assertion failure when reading from address 0. 2017-08-09 12:42:17 -07:00
Tim Newsome b897807224 When gdb_port is 0, don't increment it.
Usually incrementing to get the next port is a good idea, but when set
to 0 the idea is to find an arbitrary unallocated port. 1 is almost
certainly not helpful.
2017-08-07 13:55:37 -07:00
Tim Newsome 46b5f913c7 Display register numbers in a more usable format. 2017-07-27 13:45:26 -07:00
Tim Newsome 753d15e22c Print out which port OpenOCD is listening on.
This is essential when a test environment asks OpenOCD to listen on port
0, so that the environment can easily discover which port is actually
being used.
2017-07-25 14:08:10 -07:00
Tim Newsome b032eb1bcc Use a wall clock timeout to complete reset. 2017-07-16 11:48:12 -07:00
Tim Newsome f0f1df1061 Fix infinite loop in reset. 2017-07-14 12:50:11 -07:00
Megan Wachs c8015e8dc1 riscv compliance: More post-test cleanup 2017-07-13 08:00:22 -07:00
Tim Newsome d60dbd60e8 Share trigger code between 0.11 and 0.13 code.
The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.

In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
Megan Wachs 20d46b8bf0 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-07-12 18:46:26 -07:00
Megan Wachs 66fa38add7 riscv-compliance: Halt harts again at the end of the test. 2017-07-12 18:44:41 -07:00
Tim Newsome 2deb02695e Forgot to commit this follow up to PR #79 2017-07-12 17:51:38 -07:00
Tim Newsome 09bf86e31a Keep around cmderr for callers to inspect.
Use this to only change abstract register access behavior when cmderr
explicitly says the requested operation is unsupported.
2017-07-12 14:36:09 -07:00
Tim Newsome 856f70fe44 Try abstract register writes as well. 2017-07-12 14:13:31 -07:00
Tim Newsome f37e93bbc0 Try using abstract commands to read registers
This is the only way the spec guarantees that GPRs are accessible, and
depending on the implementation this might be the only way that CSRs are
accessible.

Also changed the debug code that parses out DMI fields to be simpler to
maintain (albeit a little slower).

riscv013_execute_debug_buffer() now automatically clears cmderr if the
command fails. That feels like the right behavior. (It does return the
error to its caller.)
2017-07-12 14:13:31 -07:00
Tim Newsome da74f511b9 Merge pull request #80 from riscv/triggers
Disable debugger-set triggers on connect
2017-07-11 12:13:56 -07:00
Palmer Dabbelt 10a61000b5 Use LL for 64-bit defines, as Windows is LLP64
This should also fix bugs on ILP32 systems.
2017-07-10 13:45:42 -07:00
Tim Newsome 4072fa493b Disable debugger-set triggers on connect
When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.

To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.

Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
2017-07-10 10:26:24 -07:00
Tim Newsome 21e06e1d89 Fix 32-bit build.
Code taken from http://openocd.zylin.com/#/c/4178/
2017-07-06 14:53:28 -07:00
Tim Newsome 31e5b53a46 Merge pull request #74 from riscv/build32
Fix 32-bit build errors.
2017-07-06 13:41:47 -07:00
mwachs5 6842fd2c10 riscv: Add more TODO compliance comments 2017-07-05 17:59:30 -07:00
mwachs5 bdc38561c0 riscv: Clean up reset/dmactive/step compliance test 2017-07-05 17:54:55 -07:00
mwachs5 2b94888100 riscv: Add single-step, reset, and dmactive to the compliance test. 2017-07-05 15:11:40 -07:00
mwachs5 87abbe4a51 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-07-05 11:02:30 -07:00
Tim Newsome 321619946b Merge pull request #73 from riscv/old_triggers
Add back support for type 1 triggers
2017-07-03 13:52:16 -07:00
Palmer Dabbelt 3cff4213a4 Merge pull request #69 from riscv/multi-gdb
Fix the multi-GDB mode bugs
2017-07-03 13:18:06 -07:00
Tim Newsome 450307b66f Fix 32-bit build errors.
I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes #71.
2017-07-03 12:17:07 -07:00
Tim Newsome f18fd83ac7 Fix trigger set/clear bug. 2017-07-03 11:52:35 -07:00
Tim Newsome 6c627e9ea9 Add back support for type 1 triggers.
They were implemented, and people want to keep using them.
Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the
current address of 0x301.
Actually return an error when we fail to read a CSR.
Tweak cache_set32() debug output.
2017-07-03 11:01:10 -07:00
Dmitry Ryzhov 99a3673507 Fix comment about saving the temporary register in examine procedure. 2017-07-01 15:09:23 +03:00
Dmitry Ryzhov 7d451e00f5 Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction. 2017-06-30 19:15:58 +03:00
Megan Wachs 8dc3c0a55c riscv: correct libjaylink version 2017-06-28 19:44:18 -07:00
Megan Wachs 7bc23c7776 riscv: Add some comments on what else compliance test needs 2017-06-28 19:36:22 -07:00
Megan Wachs 434fb3708a riscv: Correct DPC masking in compliance test. 2017-06-28 19:36:22 -07:00
Megan Wachs e32a8c911d riscv: Fix AUTOEXEC test for 32-bit cores 2017-06-28 19:36:22 -07:00
mwachs5 4101740928 riscv: add compliance tests for DPC and DCSR 2017-06-28 19:36:22 -07:00
mwachs5 e17ca3a31d riscv: More compliance tests for core registers. 2017-06-28 19:36:22 -07:00
mwachs5 222850df55 debug: add a 'wfi' to compliance test. 2017-06-28 19:36:22 -07:00
mwachs5 9e76ec1779 riscv: Compliance test for HALTREQ/RESUMEREQ R/W 2017-06-28 19:36:22 -07:00