this new device has the following features:
- single core cortex-M7
- 2MB flash - dual bank
- page size 8k
- write protection grouped by 4 sectors
- write block size 128 bits (16 bytes)
the bit definition of FLASH_CR is different than STM32H74x,
that's why we introduced a helper to compute the FLASH_CR value
Change-Id: I4da10cde8dd215b1b0f2645f0efdba9d198038d1
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5441
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Fix comment of tested errors in asm src.
List all relevant errors in FLASH_ERROR mask: FLASH_PROGERR was missing
and any trial to re-program already programmed double word ended up
in the error bit held uncleared and flash write permanetly repeating
the error message until reset.
Lock the bank also after unsuccesfull write_block run.
Set async target algo block size to size of double word.
Remove warning in case of write_block success. In case of error
use LOG_ERROR instead of warning.
Change-Id: Ibf6d5e306a4c2eaa43de67d636b4902c737f02f3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5360
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4
The second core creation is only done when
* DUAL_CORE variable is set to true
* non HLA interface is used
A second check for the second core existence is done in cpu1 examine-end
Once the second core is detected it gets examined.
Furthermore, the script provides a configurable CTI usage in order to halt
the cores simultaneously.
Tested on Rev X and V devices.
PS: the indentation was a mix of spaces and tabs, all changed to tabs.
Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5130
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Based on RM0433.rev5 > Section 3.3.9 : Flash program operations:
QW1/2: this bit indicates that a write, erase or option byte change
operation is pending in the write queue or command queue buffer.
It remains high until the write operation is complete.
It supersedes the BSY1/2 status bit.
On this basis, stm32x_wait_status_busy is renamed accordingly to be
'stm32x_wait_flash_op_queue'
Note : In this commit there is a fix of SR_ERROR_MASK value in flash loader algo
Note : This modification is mandatory for revision X, and backward compatible
with old revisions
Change-Id: I59d2973317d76b01fbb0fb5e4a472a47d0a7a5b5
Signed-off-by: Laurent LEMELE <laurent.lemele@st.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/4883
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Flash loaders refactored to the new style - use generated .inc
instead of hexadecimal machine code in the flash driver source.
Change-Id: If65a2099589e210f9450819b467d67819fd841fc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4439
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tarek BOCHKATI
Tomas Vanek