Add configuration for the Renesas R-Car R8A7791 M2W target.
This is an SoC with two Cortex A15 ARMv7a cores, both cores
are supported.
This patch is based on initial submission by Adam Bass and
improvements by Niklas Söderlund.
Change-Id: I297da62b9ce71ad222a401d98e6bcb8502427673
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Adam Bass <adam.bass@renesas.com>
Cc: Niklas Söderlund <niklas.soderlund@ragnatech.se>
Reviewed-on: http://openocd.zylin.com/4485
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This also fixes the transport_is_hla FIXME.
Change-Id: I33960f373f11e3e203f9aed9c6d02bf7ca48ac97
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4473
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Use sector sizes instead of bank size.
Detect a gap between sectors and emit xml blocks accordingly.
Detect sector overflow over the bank size.
Change-Id: If0e0e44b0c3b93067b4d717c9c7b07c08582e57b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4436
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Structures rtos_standard_Cortex_M4F_stacking and
rtos_standard_Cortex_M4F_FPU_stacking in rtos_standard_stackings.c
where using rtos_standard_Cortex_M3_stack_align for the stack-align
function. This function calls rtos_Cortex_M_stack_align with
XPSR_OFFSET = 0x3c. This offset is correct for cortex-M3 but not for
cortex-M4F and cortex-M4F with fpu. This patch adds stack_align
functions for M4F an M4F_FPU
Change-Id: If6a90b1898fccbb85619a10f3aef5277dd88ce47
Signed-off-by: Armin van der Togt <armin@otheruse.nl>
Reviewed-on: http://openocd.zylin.com/4037
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
On SMP targets, the "target smp" command creates a list of targets
that belong to the SMP cluster. Free this list when a target gets
destroyed on shutdown. For simplicity, the complete list is free'd as
soon as the first target of the SMP cluster is destroyed instead of
individually removing targets from the list.
Change-Id: Ie217ae1efb2e819c288ff3b1155aeaf0a19b06be
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4481
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
apcsw command was limited to SPROT bit only.
Now user can manipulate any bit except size and addrinc fields.
Can be used e.g. to set bus signal 'cacheable' on Cortex-M7
Change-Id: Ia1c22b208e46d1653136f6faa5a7aaab036de7aa
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4431
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
With this option enabled (it's disabled by default) errors accessing
registers are returned to gdb. Otherwise they are ignored and success is
reported to gdb. (This is the current behavior.)
We want this for RISC-V, but there's still some cleanup that needs to be
done before that can be upstreamed.
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I7e56109ea52d18b780c14a07fb35f9e6e8979da4
Reviewed-on: http://openocd.zylin.com/4452
Reviewed-by: Steven Stallion <sstallion@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
The CTRL/STAT register in the ARM DAP DP has a debug power up
ack bit and a system power up ack bit. Some devices do not set
the system power up ack bit until sometime later. To avoid having
the initial target examination fail due to this or to have a
sticky bit error report claim power failure due to this a user
can now specify that this bit should be ignored.
Change-Id: I2451234bbe904984e29562ef6f616cc6d6f60732
Signed-off-by: Eric Katzfey <eric.katzfey@mentalbee.com>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3710
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This saves us from re-reading s0 before doing just about anything
program buffer related.
Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.
Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
Add option "nvmuserrow" to "at91samd" for changing and reading the register at 0x804000 which represents various fuses.
Change-Id: I6382cc4ac15e6b9681e2f30b0ae60397a6289c3b
Signed-off-by: Stefan Arnold <sarnold@sh-sw.de>
Reviewed-on: http://openocd.zylin.com/4260
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
HWID originally added in commit 7829f31a6d
was accidentally omited during refactoring in commit
52885d2b53
While on it move old ingeneering sample of 51822 to block of 51822 rev 1
Change-Id: Ie9f15563792a27a72e71df6edbcc6b04490370ed
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4437
Tested-by: jenkins
KitProg firmware does not send a zero length packet at the end of the bulk-in
transmission of a length divisible by a bulk packet size. This is inconsistent
with the USB specification and results in jtag_libusb_bulk_read()
waits forever when a transmission of specific size is received.
Limit bulk read size to expected number of bytes for problematic tranfer sizes.
Use 1 second timeout as the last resort.
Change-Id: Ice80306424afd76e9fbc6851911ffd5109c84501
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4426
Tested-by: jenkins
Reviewed-by: Bohdan Tymkiv <bhdt@cypress.com>
Avoid ever overflowing the DWT_COMPARATOR array by allocating space for
16 comparators (the field is masked by 0xf).
On a stm32f767zi chip (on a nucleo-767zi board) I've been seeing crashes
with address sanitizer enabled due to its (apparent) 10 present
comparators. This appears to be due to
https://sourceforge.net/p/openocd/tickets/178/.
In non-address sanitizer builds, this would likely cause some random
memory to be written to in some cases. (see above bug for observations).
Change-Id: I2b7d599eb326236dbc93f74b350c442c9a502c4b
Signed-off-by: Cody P Schafer <openocd@codyps.com>
Reviewed-on: http://openocd.zylin.com/4458
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
All drivers which simply allocate one driver_priv memory block
per each bank now use default_flash_free_driver_priv()
Change-Id: I425bf4213c3632f02dbe11ab819c31eda9b2db62
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4417
Tested-by: jenkins
Reviewed-by: Liviu Dudau <liviu@dudau.co.uk>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.
This fixes#194.
Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
This replaces the earlier mechanism which would propagate errors only
for targets that decided they wanted to. It was suggested by Matthias
Welwarsky from the OpenOCD team.
Change-Id: Ibe8e97644abb47aff26d74b8280377d42615a4d3
If the target is held in reset we'd keep adding more delays, and since
those grow exponentially they'd get so huge it would take forever to
exit out of the loop.
Change-Id: Ieaab8b124c101fd1b12f81f905a6de22192ac662
Most Xilinx FPGA devices contain an embedded, unique device identifier.
The identifier is nonvolatile, permanently programmed into the FPGA, and is
unchangeable providing a great serial / tracking number.
This commit adds generic support for reading the Xilinx Spartan 6 and 7
Series (Kintex, Artix, Ultrascale) Device DNA. The code is similar to
the function in fpga/xilinx-xc6s.cfg for Spartan 6 but the register
addresses are different and the logic has been simplified.
The code was not placed in xilinx-xc7.cfg. The approach of defining taps
in the same file as library code to use them is fundamentally broken on
boards that have more than one FPGA or other chips. This commit (like
the addition of support for Xilinx XADC) starts to remedy that by
splitting library code from board-specific fixed definitions.
The support code is sourced in the Kasli and KC705 board support files
as it was tested on these boards.
Change-Id: Iba559c7c1b7e93e1270535fd9e6650007f3794da
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4396
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
temperature, internal power supply rail voltages as well as external
voltages. The XADC is available both from fabric as well as through the
JTAG TAP.
This code implements access throught the JTAG TAP.
https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
Change-Id: I6cef4d0244add71749fa28b58a736302151cc4dd
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4395
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Also call adapter_exit() before command_exit() as the latter releases
Jim interpreter so JTAG events should be released before.
Fixes memory leak reported by valgrind
Change-Id: I493f3fcba34ea2b4234148e79a4e329c866e0f05
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4474
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
If a target is run from gdb and then stopped from OpenOCD telnet interface,
halt does not show message with status and PC registers.
While on it rename 'display' to 'verbose_halt_msg' and use bool type
instead of int.
Change-Id: Ibe6589015b302e0be97258b06938c297745436a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4475
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Kasli is an open hardware FPGA board. It is part of the Sinara family of
devices designed to control quantum physics experiments (see Sayma_AMC
for other boards already suppported by openocd).
Kasli was developed as part of the opticlock project. It features a
Xilinx Artix 7 100T FPGA, DDR3 RAM, a clock reconstruction and
distribution network, four 6 Gb/s transceiver links (three SFP and
one SATA) as well as interfaces to up to 12 Eurocard Extension Modules
(EEMs).
https://github.com/m-labs/sinara/wiki/Kaslihttp://www.opticlock.de/en/
Change-Id: I88b5e9f16b79e1e731056c45da6b5e1448d2c0e7
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4341
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tim Newsome
Niklas Söderlund
Ryan Macdonald
Paul Fertser
Tomas Vanek
Armin van der Togt
Matthias Welwarsky
Stefan Arnold
Cody P Schafer
Michele Sardo
Robert Jordens