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Author SHA1 Message Date
Evgeniy Naydanov 5a29a7399f target/riscv: refactor register accesses 
Change-Id: I45731d501f6261c4142c70afacf3fbbe42cf2806
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
 2023-05-23 20:20:19 +03:00
Evgeniy Naydanov c822dc8194 target/riscv: improve register caching (prep_*, cleanup_*) 
Introduce riscv_write_register to prep_for_register/vector_access and
cleanup_after_register/vector_access.

Change-Id: I77a0a06ac6f12eceec309f0aff94aa77bd56ff55
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
 2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 8f3a617dc7 target/riscv: improve register caching (riscv_write_register) 
This commit introduces a new function, which can be used to reduce number
of register accesses.

Change-Id: I125809726eb7797b11121175c3ad66bedb66dd0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
 2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 7a181e8bbc target/riscv: use `riscv_reg_t` and `enum gbb_regno` consistently 
Change-Id: Ia476251e835fa5fd129ae6b679c6049c5c60c716
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
 2023-05-22 11:55:37 +03:00
Evgeniy Naydanov 919a98a05b target/riscv: fix register cache flushing 
Since writing a register can make some GPRs dirty (e.g. S0, S1), registers
should be flushed in reverse order, so GPRs are flushed last.

Change-Id: Ice352a4df4ae064619c0f9905db634a7b57e4711
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
 2023-05-22 11:55:37 +03:00
Tim Newsome 461eb65e21
Merge pull request #847 from riscv/data1_cache 
target/riscv: Comment that data1 might change.
 2023-05-18 10:56:00 -07:00
Tim Newsome be5187d0a8 target/riscv: Comment that data1 might change. 
In case in the future I have the same idea of optimizing progbuf writes
again.

Change-Id: Ie383487691cceeff75e2c22f4c85fc1fe4873937
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-05-17 09:46:23 -07:00
Tim Newsome 0a38258f71
Merge pull request #848 from riscv/removed-unused-func-set-frontend-running 
gdb_server: Removed unused function gdb_set_frontend_state_running
 2023-05-16 09:28:14 -07:00
Tim Newsome d78d991191
Merge pull request #850 from riscv/cleanup-in-target-c 
Minor cleanup in target.c
 2023-05-16 09:27:57 -07:00
Tim Newsome 15bd33cc20
Merge pull request #844 from riscv/from_upstream 
Merge 228fe7 from upstream
 2023-05-15 08:17:31 -07:00
Jan Matyas bd275ef483 Minor cleanup in target.c 
Small cleanup in target.c to get rid of few upstream differences:

- removed a pointless check for `reg->exists` - already checked
  few lines above
- unify one log message with what's in upstream

Change-Id: I3fd761157382670611fa90de84e2dfc90192f473
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
 2023-05-15 15:09:55 +02:00
Jan Matyas 528970c47a gdb_server: Removed unused function gdb_set_frontend_state_running 
Non-functional change: unused function removed that does not exist
in the OpenOCD upstream, either.

Change-Id: Ibeab5b41a24183673cc02ca919b2f7285309e6f4
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
 2023-05-15 12:38:02 +02:00
Tim Newsome 57d20e4d96 target/riscv: Remove non-functional code in riscv_program_exec(). 
Addresses #845.

Change-Id: If4eee383f92946669a84f92e52a3ac3600707525
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-05-10 16:58:09 -07:00
Tim Newsome da44fb5407 Merge commit '228fe7300c7df7aa05ba2c0bc19edde6d0156401' into from_upstream 
Conflicts:
	doc/openocd.texi
	src/jtag/aice/aice_pipe.c
	src/jtag/aice/aice_usb.c
	src/rtos/FreeRTOS.c
	src/rtos/hwthread.c
	src/rtos/rtos_standard_stackings.c
	src/target/riscv/riscv.c

Change-Id: I0c6228c499d60274325be895fbcd8007ed1699bc
 2023-05-04 14:38:10 -07:00
Tim Newsome 80d529cad3
Merge pull request #843 from riscv/hypervisor_translate 
target/riscv: Support hypervisor address translation
 2023-05-04 09:52:54 -07:00
Tim Newsome 880fa0a8da target/riscv: Support VS-stage and G-stage address translation. 
These are used in hypervisor mode.

Change-Id: I5f773816f73c83b4ae57727fbc3b36b65b6185eb
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-04-28 14:48:49 -07:00
Tim Newsome fc52bfefc8
Merge pull request #840 from aap-sc/aap-sc/resume_on_bp 
fix bp handling during resume
 2023-04-28 09:13:58 -07:00
Parshintsev Anatoly 152ef1a936 fix bp handling during resume 
Depending client parameters OpenOCD resume command can do step+resume
to avoid triggering a pending breakpoint

Change-Id: Ib7ae544e1a1f13843584f4c1c87db17851642b89
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
 2023-04-27 10:06:08 +03:00
Tim Newsome d4429f62e4 target/riscv: Refactor to create riscv_effective_privilege_mode() 
Change-Id: I65bba63a7bde746b0069133f8a42529d1d857d3e
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-04-25 10:58:24 -07:00
Tim Newsome 5da1e086b6 target/riscv: Move some code from riscv_address_translate() to riscv_virt2phys() 
Also minor code cleanups, and better debug messages.

Change-Id: Iffc9951c8b38da2e3516926108b93db91883680e
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-04-25 10:35:12 -07:00
Tim Newsome 85f44fc37f Comment pte_shift 
Change-Id: I48ad7637ff37898ca2df0f48501cf2c72fa1e722
 2023-04-25 09:34:27 -07:00
Tim Newsome f2c2ebbcd0 target/riscv: Add constants for vsatp, hgatp 
Change-Id: I130a8f7a7abc294bbdf60e7e0ce0bccb72bf920a
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-04-25 09:30:27 -07:00
Parshintsev Anatoly 7ca8350d3a target/riscv: respect error code from dm013_select_target in select_prepped_harts 
Change-Id: I3099589521538590e366d60629e49cfc74e2d0c6
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
 2023-04-24 21:15:56 +03:00
Tim Newsome c454db3eee
Merge pull request #835 from en-sc/en-sc/fix-err-resume 
target/riscv: Handle error code in resume_prep
 2023-04-11 09:54:47 -07:00
Tim Newsome da229508aa
Merge pull request #833 from zqb-all/read_log128 
target/riscv: support log memory access128 for read
 2023-04-11 09:53:48 -07:00
Evgeniy Naydanov 08df077083 target/riscv: Handle error code in resume_prep 
If hart can't change pc (e.g. it is running), resume command should
fail.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I14627366d574d806ea16262b7d305d8161f8bcc2
 2023-04-10 17:19:20 +03:00
Mark Zhuang aa7344225b target/riscv: support log memory access128 for read 
Change-Id: I9235150fa00c03a1d75d0b44a7500758daa56e2b
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
 2023-04-10 09:48:48 +08:00
Tim Newsome 0c76e263e3
Merge pull request #823 from panciyan/riscv 
target/riscv: leaf PTE check PTE_W missing
 2023-04-07 10:05:57 -07:00
Tim Newsome 15bb3e23b8
Merge pull request #821 from en-sc/en-sc/fix-reset-mharts 
target/riscv: simplify reset for rtos harts
 2023-04-06 09:54:15 -07:00
Tim Newsome 52b102318b
Merge pull request #830 from zqb-all/csr_32bit 
target/riscv: set some csr size to 32
 2023-04-06 09:40:59 -07:00
Tim Newsome 7e36bb6158
Merge branch 'riscv' into hypervisor 
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-04-05 10:48:56 -07:00
Evgeniy Naydanov 1c168242e9 target/riscv: simplify reset 
Since the deletion of `-rtos hwthread`, there is no need to treat harts
with `-rtos` specified differently on reset.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I88a9129936b5172bb7479dfa1255e29ff460c054
 2023-04-05 19:14:45 +03:00
Tim Newsome c6ba4166e4
Merge pull request #816 from riscv/from_upstream 
Merge up to commit '1293ddd65713d6551775b67169387622ada477c1' from upstream
 2023-04-05 08:47:27 -07:00
Tim Newsome 2dc14117a7
Merge pull request #819 from zqb-all/fix_size_assert 
target/riscv: support log memory access128
 2023-04-04 11:05:52 -07:00
Tim Newsome d031d501cd flash/nor/spi: Move mt25ql02 to match upstream. 
Change-Id: I7537c122d581ec1848a1e7902874506e0bbb6e31
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-04-04 10:51:29 -07:00
Mark Zhuang e284aa066e target/riscv: set some csr size to 32 
Change-Id: I4703b7b8ad492b14dc8d188ebb8f645c568fd515
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
 2023-04-03 23:53:14 +08:00
Tim Newsome 38cf11abab
Merge pull request #824 from riscv/aia 
target/riscv: AIA regs, check for H not V
 2023-03-29 13:52:34 -07:00
Tim Newsome 4fdcc14e26 target/riscv: Set hypervisor bits. 
No other attempt is made at doing anything hypervisor-specific. Are
other things necessary?

Change-Id: Ib65f114888840cf0878f9bfe028c9a42b436aa3f
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-03-29 13:40:39 -07:00
Mark Zhuang dfce1d2708 target/riscv: [NFC] rename variables named read/write 
read/write is system function

Change-Id: I75db4dd5a1c60e9cff8a58a863a887beffc37cab
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
 2023-03-25 21:18:12 +08:00
Mark Zhuang 4cccda353c target/riscv: support log memory access128 
Change-Id: I6b22c97f81fac26703b66d3dbd8b6d41aaea4875
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
 2023-03-25 20:31:42 +08:00
Tim Newsome 5bc9c207eb target/riscv: Don't ignore maskmax for icount. 
Icount triggers don't have a maskmax field at all. This is a cut and
paste error.

Change-Id: I001b3d41bf683599706dba713f7be475e8dd1668
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-03-24 13:41:06 -07:00
Tim Newsome 194a90186c target/riscv: AIA regs, check for H not V 
Change-Id: Iac37b79dc737fd64a21dce83b3ef36f1a8aae118
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-03-24 09:21:48 -07:00
panciyan 1479eca38f target/riscv: leaf PTE check PTE_W missing 
When permission bits R, W, and X in PTE all three are zero,
the PTE is a pointter to the next level of the page table;
otherwise, it is a leaf PTE. Here PTE_W is missed.

Change-Id: I82a4cc4e64280f0fcad75b20e51b617520aff29b
Signed-off-by: panciyan <panciyan@eswincomputing.com>
 2023-03-23 02:45:42 +00:00
Tim Newsome d744207943
Merge pull request #815 from riscv/s_aia 
target/riscv: Expose S?aia CSRs if they're on the target.
 2023-03-20 08:45:13 -07:00
Tim Newsome 1c07a207e3 gdb_server: Keep working if gdb requests a non-existent reg 
Change-Id: Ica55a227f7df4f0606fa1ac071bca172411e9230
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-03-17 09:48:41 -07:00
Tim Newsome 2cd3436002 Fix build. 
Change-Id: I89de7dc21d7958531ec9619905d3d8c4f54a3acf
 2023-03-16 18:08:25 -07:00
Tim Newsome 868ebdd89c Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream 
This includes
https://sourceforge.net/p/openocd/mailman/message/37710818/, which
should fix #814.

Conflicts:
	.travis.yml
	contrib/loaders/flash/stm32/stm32f1x.S
	contrib/loaders/flash/stm32/stm32f2x.S
	doc/openocd.texi
	src/rtos/FreeRTOS.c
	src/server/gdb_server.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg
	tcl/target/gd32vf103.cfg
	tools/scripts/checkpatch.pl

Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
 2023-03-16 18:02:35 -07:00
Tim Newsome 3387015af0
Merge pull request #800 from en-sc/en-sc/try-all-trigs-in-maybe-add-trig 
Try all triggers in maybe_add_trigger_t*
 2023-03-16 16:58:12 -07:00
Tim Newsome 2c760b6317 Expose S?aia CSRs if they're on the target. 
Untested, because I don't have a target that implements this.

Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a
Signed-off-by: Tim Newsome <tim@sifive.com>
 2023-03-16 15:37:06 -07:00
Tim Newsome eb8cabf821 Update encoding.h. 
Change-Id: I1b6d2cac86ec485310761b73370fb2667ebb3bbd
 2023-03-16 11:27:06 -07:00