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2613 Commits

Author SHA1 Message Date
Megan Wachs 3a1d6f1702 riscv: Add register name to message when they do not exist. 2017-02-10 14:19:23 -08:00
Megan Wachs 7b95554ff5 Merge remote-tracking branch 'origin/riscv' into HEAD 2017-02-07 11:24:12 -08:00
Tim Newsome 075c0e80d1 Add debug_defines.h. 
Change-Id: I94753f9bed11cbc978daa0f3ea3ecf2023b93893
 2017-02-09 09:57:54 -08:00
Tim Newsome 2ad366e658 Detect and smoketest data and ibuf registers. 
Change-Id: I7ee4817ec63041a1577b83392d40b676fb67c207
 2017-02-08 20:40:37 -08:00
Tim Newsome 8cac7d0cee Correctly parse dmcontrol. 
Change-Id: Ibae425f4ccbe9e504c41e185f264f667e091fca4
 2017-02-08 19:47:34 -08:00
Tim Newsome 8af4a9a053 Update DMI bus width for 0.13. 
Change-Id: Ieff13a7a0084fe822b7cc6d927727eba4f158ef0
 2017-02-07 11:28:50 -08:00
Tim Newsome ecc5b6ecad Add missing header file. 
Change-Id: I19df5112c2503ec6652f2d09e7324180af5024df
 2017-02-05 21:32:44 -08:00
Megan Wachs 2ae0078fc7 Use the set/reg register error return code when registers don't exist. 2017-02-05 21:06:43 -08:00
Tim Newsome 6f78eb1ec1 Add the first difference for 0.13 targets. 
Just to confirm the 0.13 code takes a different path.

Change-Id: I7f1c9c8f3b586aee001dbeef2213f5f2e6a94f36
 2017-02-05 18:21:34 -08:00
Tim Newsome 8d195afd2d Use the csrNNN name instead of "mstatus". 
Fixes flashing code.

Change-Id: Id12c926f5ada009e06f6601362deefec946afc98
 2017-02-05 18:19:00 -08:00
Tim Newsome d055f86552 Most gdbserver tests pass now. 
Change-Id: I14a8360d9cf2800ca5e6a44f7e58102b2baef719
 2017-02-05 18:09:19 -08:00
Megan Wachs 5d82a395f1 riscv: disable interrupts for all priviledge levels 2017-01-25 21:51:02 -08:00
Megan Wachs d5892f0ee5 riscv: Use proper UINT packing and unpacking routines for disabling interrupts before running algorithms. 2017-01-25 15:23:10 -08:00
Megan Wachs 5766efe0c3 riscv: Globally disable interrupts when running algorithms. 2017-01-25 11:35:57 -08:00
Megan Wachs 4a0d3fb035 riscv: implement skeletons for Memory Blank Check and CRC. Otherwise you just get a segfault when attempting to perform these actions. 2016-12-07 15:09:35 -08:00
Tim Newsome c1da323144 Fix issue #6: build failure on gcc 6 
Change-Id: If890a6d62fdd55befb9057f83726f60721ac8078
 2016-12-01 19:15:55 -08:00
Tim Newsome 7dd48acdc0 Cope better if the target unexpectedly resets. 
Change-Id: I713f7f8a3afbbb02be0e2f19f4d32778366d37f9
 2016-11-25 09:46:55 -08:00
Tim Newsome 8ee0647365 Flash at 8KB/s, using 10,000 byte working area. 
If the working area is large enough, every fespi_write() results in just
a single algorithm execution.

Change-Id: I87a12e29f50ef6ea1f46fbd1edf440f9e54a2162
 2016-11-18 10:58:26 -08:00
Tim Newsome c406b4530e Merge branch 'Og' into enable_flash_prog 2016-11-17 13:44:35 -08:00
Tim Newsome 18eedf996c Use algorithm to speed up fespi flash programming. 
It's still really slow, at 854b/s, but it seems to work and it's a lot
of new code.

Change-Id: I9dd057bbcc81a56eb558b4f33ac35f6f03c23588
 2016-11-16 17:54:55 -08:00
Tim Newsome e51b0360f5 Make fpu regs work even if mstatus.fs is 0. 
Change-Id: I2c283f2de226518ab9a4e0476edada51825b2993
 2016-11-01 12:58:37 -07:00
Tim Newsome e7a745ed3b Fix bug with slow targets. 
Halting didn't work right in slow targets, because some code assumed the
register cache is valid before it was guaranteed to be.

Also made dbus_busy_delay and interrupt_high_delay grow faster, so that
on slow targets it takes less time to learn the correct values.

Change-Id: I948a49d4e3cd0638f5449ab94994406319fd5f42
 2016-10-27 13:00:26 -07:00
Tim Newsome e6e2070692 Add some comments. 
Change-Id: Icd7d5eb370c6c893ec4717c92249f35fb100370a
 2016-10-24 14:21:34 -07:00
Tim Newsome 3eb6cf0fc0 Make CLI step and resume work. 
Change-Id: I027d7032800f909e8d149ed84c11b6e75b75491f
 2016-10-20 14:49:23 -07:00
Tim Newsome 9b0be80d1e Use reg_cache structure, to make reg command work. 
Change-Id: I9f1d1f2eab66822c3c47284aa91b52cc34998381
 2016-10-20 10:42:28 -07:00
Tim Newsome 4eba841bfe Print when we're ready for gdb to connect. 
This should help gdbserver.py to connect reliably to really slow targets
(ie. simulators).

Change-Id: I8e9adbaf2ebde11b44e15582f036622a2d00c1f9
 2016-10-14 12:40:52 -07:00
Tim Newsome 3f6c2a9f78 Be quiet when the target is just running normally. 
Change-Id: I7861f16ba6b1b5c1851787ce5d78c02aff0568f6
 2016-10-13 10:51:53 -07:00
Tim Newsome cb93bb9035 Use an easily changed constant for timeout. 
Change-Id: I7aace463b0bd9916580e950d60b2940879b27b2a
 2016-10-11 16:26:19 -07:00
Tim Newsome 4882de94cc Display pc to the user in 'monitor reset init'. 
Change-Id: Ifb8df31954dfc5a3badef4f0a29eb510a97310a2
 2016-10-10 08:22:51 -07:00
Tim Newsome 80e8101292 Make OpenOCD build using -Og. 
With -Og gcc doesn't perform as many optimizations, and as a result
warns about some code that it wouldn't otherwise warn about.

These fixes all assign values to otherwise uninitialized variables.

Change-Id: I9a6ea5eadd73673891ecfec568b8b00d78b596a5
Signed-off-by: Tim Newsome <tim@sifive.com>
 2016-10-04 10:02:42 -07:00
Tim Newsome a08cef7633 Change invalid access from error to user message. 
It's not a failure in the debugger or even a real problem if a user asks
to access memory that's not accessible.

Change-Id: I30b8424d5265d1996fe4826012ed160a83f0bc6c
 2016-10-03 08:15:04 -07:00
Tim Newsome e273e23f41 Fix off-by-one error in assert. 
Also only do work for debug RAM that actually exists on the target
(exposing the off-by-one error on 32-bit targets).

Change-Id: I37e0005b6a70e949286f1d6494716f3abea03c12
 2016-09-29 10:40:50 -07:00
Tim Newsome 4dbc9962d3 Clear dmode triggers when we first halt the target 
This helps repeated runs of the testsuite pass, and is probably a good
idea in general.

Change-Id: I89ed167968f8b8817c66f1718f374d0c502780c7
 2016-09-29 10:23:46 -07:00
Tim Newsome 78fe0b56db Deal with dbus being busy in all cases. 
Change-Id: Ifede6e05c3c4538f22a52cd0e9833cf3a9983d04
 2016-09-29 08:28:31 -07:00
Tim Newsome b04d5e8821 Read idle, and test all debug RAM. 
Read dtmcontrol's idle field to decide how many run-test/idle cycles are
required to communicate with the target.

In riscv_examine(), write and read all of Debug RAM to check the target
is at least somewhat sane.

Change-Id: Ieedb7a50418fa1f5e0d456cde53c52f7fc51662b
 2016-09-27 13:06:32 -07:00
Tim Newsome c67850b63d Only write to existing dram. Clear dbus error. 
Old code would write 64 bytes of DRAM if the dbus was busy in
cache_write().

New code clears the dbus error condition when the bus is busy. (This
part is untested.)

Change-Id: Ia396fe819fa1828bb75726d85513b113cc9e13f0
 2016-09-27 08:45:51 -07:00
Tim Newsome 54c65a9a4b Improve low-level logging. 
Now logging is consistent and more readable.
I did remove most logging during riscv_poll() since it clutters up the
log/screen and is not generally helpful.
 2016-09-23 14:16:24 -07:00
Tim Newsome 08228e6f53 Make more code use the scans "class". 
Helps with consistency, and this is a rare commit that net deletes
lines.
 2016-09-23 14:16:24 -07:00
Tim Newsome cf1dc0b6cb Implement hardware triggers that match spec. 
It's basically working, but the following corner cases are failing:
    TriggerDmode
    TriggerLoadAddressInstant
    TriggerStoreAddressInstant
 2016-09-23 14:16:24 -07:00
Tim Newsome 526bbc5284 Optimize read a bit. 
Remove some unnecessary scans.
 2016-09-23 14:16:24 -07:00
Tim Newsome c68b13ed67 Properly mark the cache as clean after its written 
This reduces the number of scans, but I doubt it noticeably improves
performance.
 2016-09-23 14:16:24 -07:00
Tim Newsome 243233c8b8 Convert some more code for 64-bit. 2016-09-23 14:16:24 -07:00
Tim Newsome b04f89076a Properly write 64-bit PCs. 2016-09-23 14:16:24 -07:00
Tim Newsome e3e745abb9 WIP for 64-bit support. 
GPR register writes/reads seem to work.
 2016-09-23 14:16:24 -07:00
Tim Newsome 2f1b6b5803 Stop using conditional writes. 
It doesn't help, and makes the spec more complex. Now that I've proven
OpenOCD doesn't need it, I'll remove it from the spec.
 2016-09-23 14:16:24 -07:00
Tim Newsome 5dbad6b0c9 Check for business in block reads. 2016-09-23 14:16:24 -07:00
Tim Newsome f8b0f4bf29 Check for exceptions in reads and writes. 2016-09-23 14:16:23 -07:00
Tim Newsome f5ae4d864c Add support for virtual priv register. 
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
 2016-09-23 14:16:23 -07:00
Tim Newsome 5de81da8f4 Remove commented out code. 
Also added back the initial check that confirms debug RAM is written
correctly.
 2016-09-23 14:16:23 -07:00
Tim Newsome a916d204b9 Optimize memory read. 
Saves 8s on the full test suite.
 2016-09-23 14:16:23 -07:00