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Author SHA1 Message Date
Tim Newsome 3173314f28 Fix access FPU registers again. 
Not a great fix. There's still a problem with accessing 64-bit floating
point registers on 32-bit cores.
24 of the gdbserver.py tests pass now.

Change-Id: I69a88ef5fd5581e2c7bf1d78057fd474ae86ff93
 2017-02-17 19:03:32 -08:00
Tim Newsome 071f9a2916 Fix use of REG vs CSR constants. 
23 gdbserver.py tests pass now.

Change-Id: I32805d615ae5f536f179baf906e0e74a56e80c0b
 2017-02-17 12:35:43 -08:00
Tim Newsome b363d1a37e Bunch of register access refactoring. 
Got rid of the last reference to the old debug RAM code! (Mostly?)
SimpleF18Test passes now.

Change-Id: Iab51d436a50bec9a5e504df7fb3cd6be874da0be
 2017-02-17 11:53:37 -08:00
Tim Newsome 88f14f4d5e Check busy before triggering another command. 
This version was able to download code, and run to a breakpoint.

Change-Id: I0ead8350579263d8e55f8df35e2b7af6c374ef21
 2017-02-16 14:21:17 -08:00
Tim Newsome ef3875a320 Check for errors after read/write. 
The code doesn't do anything intelligent if errors are found.
But MemTestBlock now also passes. I'm not quite sure why.

Change-Id: I8512f0a96db9e34d3db6a4a9bcef6e56f191d4c1
 2017-02-15 20:41:39 -08:00
Tim Newsome 035b4dd17a Fix double read, which might have side effects. 
Now passing MemTest{8,16,32,64}

Change-Id: I286d1e2a388d41853e5aa9049490ddb6135b61f1
 2017-02-15 19:05:51 -08:00
Tim Newsome 713c001242 Make MemTest32 pass. 
Change-Id: I9be90b07be695c976380f9fd50b971f8bb94f513
 2017-02-15 17:10:53 -08:00
Tim Newsome 79e840aaa7 Some memory access works. 
MemTest16 passes, but MemTest32 fails.

Change-Id: I17fbc38b4228b27c7fb3dadb15e9c1a2f67bcd65
 2017-02-15 15:44:36 -08:00
Tim Newsome 657e844c8c Merge pull request #15 from sifive/get_set_reg_error 
Use the set/reg register error return code when registers don't exist.
 2017-02-14 17:28:10 -08:00
Tim Newsome ceb8dc048d Make general CSR reads work. 
Change-Id: Ic9b7e065b7303b3707c28c9b7c496cc1c1e91acd
 2017-02-14 12:55:03 -08:00
Tim Newsome ae4fda2719 Make it all the way through examine(). 
This includes reading GPRs (although I haven't confirmed the values) and
doing some CSR reading/writing to disable triggers that may be left over
from a previous setting.

Change-Id: I2c627bd002d601e302a40f838087541897c025fd
 2017-02-14 11:43:58 -08:00
Tim Newsome 00925574d5 More dbus->dmi. 
Change-Id: Ia691f1e7ce909da4d9c16e6d691c4f2cf768a7fb
 2017-02-14 09:38:09 -08:00
Tim Newsome 24033b53d8 Read misa during examine(), using program buffer. 
Change-Id: Icad5324d216b61207cb5f6024b2deab065658640
 2017-02-13 21:29:02 -08:00
Tim Newsome 0fa8162a8c dbus -> dmi 
Change-Id: I4c3343f8f5ffd45e3d76a2218aaa5dee8e546839
 2017-02-13 11:13:14 -08:00
Tim Newsome e2a5e02d1c Discover XLEN using abstract reg reads. 
Change-Id: Ib7480b8e4925cf08e5b59d263bcdcc672a89dc4b
 2017-02-13 09:54:05 -08:00
Tim Newsome e6221e75c9 Attempt to discover XLEN with abstract reg reads 
Change-Id: I7ce9c8c0c34bd875dba11596e6f6268320b2fb3a
 2017-02-10 19:08:44 -08:00
Megan Wachs 3a1d6f1702 riscv: Add register name to message when they do not exist. 2017-02-10 14:19:23 -08:00
Tim Newsome 5e3d9803ab Halt target in riscv_examine(). 
Change-Id: I11ab915901f2e75f9b728d6cf72c6498e3950ded
 2017-02-10 11:31:14 -08:00
Tim Newsome 075c0e80d1 Add debug_defines.h. 
Change-Id: I94753f9bed11cbc978daa0f3ea3ecf2023b93893
 2017-02-09 09:57:54 -08:00
Tim Newsome 2ad366e658 Detect and smoketest data and ibuf registers. 
Change-Id: I7ee4817ec63041a1577b83392d40b676fb67c207
 2017-02-08 20:40:37 -08:00
Tim Newsome 8cac7d0cee Correctly parse dmcontrol. 
Change-Id: Ibae425f4ccbe9e504c41e185f264f667e091fca4
 2017-02-08 19:47:34 -08:00
Tim Newsome 8af4a9a053 Update DMI bus width for 0.13. 
Change-Id: Ieff13a7a0084fe822b7cc6d927727eba4f158ef0
 2017-02-07 11:28:50 -08:00
Megan Wachs 7b95554ff5 Merge remote-tracking branch 'origin/riscv' into HEAD 2017-02-07 11:24:12 -08:00
Tim Newsome d78ee9303e Merge pull request #16 from sifive/0.13 
Refactor code to support multiple debug spec versions.
 2017-02-06 09:20:15 -08:00
Tim Newsome ecc5b6ecad Add missing header file. 
Change-Id: I19df5112c2503ec6652f2d09e7324180af5024df
 2017-02-05 21:32:44 -08:00
Megan Wachs 2ae0078fc7 Use the set/reg register error return code when registers don't exist. 2017-02-05 21:06:43 -08:00
Tim Newsome 6f78eb1ec1 Add the first difference for 0.13 targets. 
Just to confirm the 0.13 code takes a different path.

Change-Id: I7f1c9c8f3b586aee001dbeef2213f5f2e6a94f36
 2017-02-05 18:21:34 -08:00
Tim Newsome 8d195afd2d Use the csrNNN name instead of "mstatus". 
Fixes flashing code.

Change-Id: Id12c926f5ada009e06f6601362deefec946afc98
 2017-02-05 18:19:00 -08:00
Tim Newsome d055f86552 Most gdbserver tests pass now. 
Change-Id: I14a8360d9cf2800ca5e6a44f7e58102b2baef719
 2017-02-05 18:09:19 -08:00
Tim Newsome 9bab0782d3 Merge pull request #13 from sifive/disable_interrupts 
riscv: Globally disable interrupts when running algorithms.
 2017-01-26 10:45:13 -08:00
Megan Wachs 5d82a395f1 riscv: disable interrupts for all priviledge levels 2017-01-25 21:51:02 -08:00
Megan Wachs d5892f0ee5 riscv: Use proper UINT packing and unpacking routines for disabling interrupts before running algorithms. 2017-01-25 15:23:10 -08:00
Megan Wachs 5766efe0c3 riscv: Globally disable interrupts when running algorithms. 2017-01-25 11:35:57 -08:00
Tim Newsome 193f630948 Merge pull request #11 from sifive/malloc_off_by_1 
Correct off by 1 in malloc
 2016-12-24 10:14:53 -08:00
mwachs5 ddb4caf846 Correct off by 1 in malloc, which causes this to fail on macOS (and in theory on any platform). 2016-12-23 17:53:26 -08:00
Tim Newsome b474c22b33 Merge pull request #9 from sifive/increase_as_size 
riscv: Increase the number of Algorithm Steps
 2016-12-19 09:42:47 -08:00
Megan Wachs 37ca3d7810 riscv: Increase the number of Algorithm Steps 2016-12-18 12:11:48 -08:00
Tim Newsome e31dd225fa Merge pull request #7 from sifive/temp_verify_blank_check 
riscv: implement skeletons for Memory Blank Check and CRC.
 2016-12-08 13:19:00 -08:00
Megan Wachs 4a0d3fb035 riscv: implement skeletons for Memory Blank Check and CRC. Otherwise you just get a segfault when attempting to perform these actions. 2016-12-07 15:09:35 -08:00
Tim Newsome c1da323144 Fix issue #6: build failure on gcc 6 
Change-Id: If890a6d62fdd55befb9057f83726f60721ac8078
 2016-12-01 19:15:55 -08:00
Tim Newsome 52d7d49d6c Merge pull request #5 from sifive/format-warning 
Use portable format specifier for size_t
 2016-11-30 16:01:43 -08:00
Albert Ou 9601429ac7 Use portable format specifier for size_t 
This fixes a gcc warning [-Werror=format] on an i686-pc-linux-gnu host,
which defines size_t as unsigned int instead of long int.
 2016-11-30 15:06:04 -08:00
Megan Wachs db2ec672b5 Merge pull request #4 from sifive/mwachs5-patch-sckdiv 
Don't write SCKDIV when flashing
 2016-11-30 10:19:54 -08:00
Megan Wachs ce49da9947 Don't write SCKDIV when flashing 
The target may have already configured its clock to run at a higher frequency and would have set SCKDIV and other dividers at that time. Don't restore the SCKDIV to its default or the flash interface may run too fast and programming will fail.

Otherwise, the default value is fine and there is no need to write SCKDIV.
 2016-11-27 21:21:45 -08:00
Tim Newsome b8879d81a2 Add timeout to infinite loop. 
Change-Id: I7d005b4779154b4dfe8c9a26f4f0e351f426df9b
 2016-11-27 15:09:42 -08:00
Tim Newsome 364f4b5ab9 Add some timeouts that I ran into. 
Change-Id: I8eeb1c934ceead0d99dcdc618a3f8aa351119cb0
 2016-11-25 17:12:50 -08:00
Tim Newsome 7dd48acdc0 Cope better if the target unexpectedly resets. 
Change-Id: I713f7f8a3afbbb02be0e2f19f4d32778366d37f9
 2016-11-25 09:46:55 -08:00
Tim Newsome bb7dedcbaa Fix typo. 
Change-Id: If04ba1103817f772fe55659cb3b5b4533c734f2a
 2016-11-23 11:14:00 -08:00
Tim Newsome 452be58b63 Merge branch 'sifive/add_issi_flash' into riscv 2016-11-19 15:41:20 -08:00
Tim Newsome b585e2e324 Fix off-by-one error in assert. 
Change-Id: I86447c747a212175be560170378c655ac801f5a6
 2016-11-19 15:40:49 -08:00