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7868 Commits

Author SHA1 Message Date
Tim Newsome 20236ca817
Merge pull request #143 from riscv/fmv 
Fix build.
 2017-12-11 13:07:35 -08:00
Tim Newsome 0a65a6527d Fix build. 
Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
 2017-12-11 12:58:20 -08:00
Tim Newsome e50ee46a6f
Merge pull request #131 from riscv/small_progbuf 
Support program buffers that are just 2 instructions large
 2017-12-11 12:52:31 -08:00
Tim Newsome 7a6704c5c6
Merge pull request #140 from riscv/encoding 
Update encoding.h.
 2017-11-27 13:48:56 -08:00
Tim Newsome 4d5f74fbe6 Update encoding.h. 
Change-Id: Id653500aa525746e8824ff5fd2850c62c8c21c08
 2017-11-27 13:23:33 -08:00
Tim Newsome 52cdf286ca Add missing return. 
Change-Id: Ida32482903cdfd8eeb043088e84bb1f4f5ac673c
 2017-11-16 15:58:08 -08:00
Tim Newsome 9b4628c9fc
Merge pull request #127 from riscv/jtag_debug 
Clean up this JTAG debug code.
 2017-11-14 09:59:25 -08:00
Palmer Dabbelt 055a70f66f
Merge pull request #133 from riscv/no-russian 
No Russian
 2017-11-03 13:15:07 -07:00
Tim Newsome e28abf7c9e Merge branch 'riscv' into small_progbuf 
Change-Id: I1d48cb1f8448ebbf98c8bb369928d1e7a7a78c75
 2017-11-01 13:38:17 -07:00
Tim Newsome 8304e1ba47
Merge pull request #134 from riscv/compile 
Fix compile warning with gcc 6.3.0
 2017-11-01 11:04:23 -07:00
Tim Newsome 40c97cc476
Merge pull request #135 from riscv/fuller_build 
Build OpenOCD the way we expect users to build it.
 2017-11-01 10:54:52 -07:00
Tim Newsome a4472f6d66 Build OpenOCD the way we expect users to build it. 
Change-Id: I3769137bc3109b44da76f2ca689d351bb93e7832
 2017-10-31 13:21:37 -07:00
Tim Newsome 6a1690d2ec Fix compile warning with new gcc. 
Change-Id: I14ebf597f41429c0fc3ebac8da9c9f62c78fb1ae
 2017-10-27 13:42:39 -07:00
Tim Newsome db754536e8 Support 64-bit FPRs on RV32. 
Because there is no instruction that moves just half of a 64-bit FPR
to/from a GPR, we need to use scratch memory for this operation. This
code can theoretically use:
1. DMI_DATA, if it is memory mapped in the target.
2. DMI_PROGBUF, if it is writable in the target.
3. A user-configured address.

I have only tested this code very lightly. One reason is that gdb thinks
that on RV32 harts every register is 32 bits wide. Another is that this
is mostly proof-of-concept to satisfy the small program buffer code
review, which I don't want to drag out forever.

Existing tests don't realize that floating support was broken with
RV32D, and don't realize that it still doesn't work because of the gdb
problem mentioned above.

This change improves Issue #110 but there's more work to be done.

Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
 2017-10-27 13:15:22 -07:00
Palmer Dabbelt 6ba66c9503 No Russian 2017-10-26 09:32:34 -07:00
Tim Newsome f416527985 Merge pull request #132 from riscv/cleanup 
Remove unused variables.
 2017-10-26 08:14:31 -07:00
Tim Newsome 1acb128290 Remove unused variables. 
Change-Id: I678d0a65c22792895375dc6916381f81af8f83e4
 2017-10-25 13:37:56 -07:00
Tim Newsome 23bd6d08c9 Remove more unused functionality. 
Change-Id: I43283b9556c959f891a587fb39bdd1ab9206e8af
 2017-10-24 15:11:33 -07:00
Tim Newsome dbecbfee99 Add a fence after memory writes. 
Change-Id: I5137479b685f735aa573cec5d40170016c40f597
 2017-10-24 12:15:25 -07:00
Tim Newsome 59a0340261 Remove more unused code. 
Change-Id: I962660f58d948f85df6e073065e15e5d8f4a02b6
 2017-10-24 11:38:39 -07:00
Tim Newsome 8432b7cf3d Remove more unused code. 
Change-Id: Id91237c163d86e8f4d039503ca33b4ad7571ecd1
 2017-10-24 11:34:48 -07:00
Tim Newsome 3ba6d46fc2 Remove unused functionality. 
Change-Id: Ic70cebd62bbd04f7ae5566504fbb279a11de57f0
 2017-10-23 14:45:58 -07:00
Tim Newsome 5425c871c9 Properly fix memory read when encountering busy. 
Change-Id: I377054495e860076edc2f38d1cc0f11c23f98d3b
 2017-10-23 14:13:46 -07:00
Tim Newsome a3a137062d Pay attention to impebreak. 
This required updating debug_defines.h, which caused a few other small
cleanups as well.

Change-Id: I3c2cb418d7eff3093d7664c5563b2af5e8b530eb
 2017-10-18 14:21:23 -07:00
Tim Newsome 85bfab36ad Remove unused functionality. 
Change-Id: I0c1464e2e6aa12d0cb1025ed0a7c1c483e7403b7
 2017-10-18 12:47:07 -07:00
Tim Newsome 5d3f5c35d2 Still restore registers if an access failed. 
Change-Id: I11571f0926f69a34f95b4929f633fdecd3a4e810
 2017-10-18 12:32:41 -07:00
Tim Newsome 7edd9b1786 Fix FPR access. 
Change-Id: I1379de87904f1cf40b45d1a5490249e3ba90d7d0
 2017-10-18 11:47:15 -07:00
Tim Newsome a0623b2fa8 Don't crash when encountering RV64. 
Change-Id: Ie915ce830c3499919e4918ad443a5e225cf8c4d9
 2017-10-17 11:58:51 -07:00
Tim Newsome 65be0776d8 Memory read/write works if the core can keep up. 
Change-Id: Ieca50ece266fbc9d2ff16a5cc2e6b4b926ad5e6f
 2017-10-17 11:52:07 -07:00
Tim Newsome fbe2980eb7 MemTest64 passes. 
Change-Id: I75996b71c3f31025c89ef596a08e01d191405336
 2017-10-17 11:15:51 -07:00
Tim Newsome d94b38279a Memtest{16,32} pass. 
Change-Id: I15c2a4fd2bb9a7b30762d07f3b3a74d2f477746b
 2017-10-16 21:08:59 -07:00
Tim Newsome 7ec7bc32fe At least some memory writes work. 
Change-Id: I6fcf261341f10ec34df01bb844744439d02471a8
 2017-10-13 12:50:02 -07:00
Tim Newsome e7bb815e87 Register read/write might be working. 
Change-Id: I6c51d6157dde56d8cd666b4d30ec7bbc7a4bef9f
 2017-10-12 14:38:52 -07:00
Tim Newsome 94e8250713 WIP; doesn't work. 
Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
 2017-10-12 11:45:52 -07:00
Tim Newsome 77802af655 Remove duplicate progbuf size variable. 
Change-Id: I662ff84d13ecfc7faae51406a4df57a3643116f0
 2017-10-10 16:27:51 -07:00
Tim Newsome f06aaa9058 Merge pull request #123 from riscv/fast_rbb 
Add read buffer to bitbang, improving performance.
 2017-10-09 11:06:20 -07:00
Tim Newsome ed415c3cb6 Merge pull request #129 from riscv/minor_revert 
Revert this LOG_INFO to LOG_DEBUG.
 2017-10-09 11:06:08 -07:00
Tim Newsome 2da7820833 Revert this LOG_INFO to LOG_DEBUG. 
Change-Id: I75dd7667a542aa1c6ea10f97fe1e00dd1ecba69d
 2017-10-08 11:41:55 -07:00
Tim Newsome 7aafd61953 Clean up this JTAG debug code. 
Change-Id: Ie7c773b98271d11085d5e50c40b64990710de387
 2017-10-06 13:55:52 -07:00
Tim Newsome d5836dceff Merge pull request #126 from riscv/compile 
Fix compile warnings.
 2017-10-04 16:07:40 -07:00
Tim Newsome 24658db50e Fix compile warnings. 
Partly fixes #124.

Change-Id: I3a7fd65c643e40b142709806cb9fb4cc62bb955f
 2017-10-04 16:02:30 -07:00
Tim Newsome 77680cb23d Merge pull request #125 from riscv/cleanup 
Revert ae74097f (extra ftdi debug).
 2017-10-04 15:48:34 -07:00
Tim Newsome 916759e0de Revert ae74097f (extra ftdi debug). 
Instead it makes more sense to push the debug changes to jtag/core.c.

Change-Id: I73bafa2a054e1f72b7752cfbce9ffc14303fc4c4
 2017-10-04 15:44:07 -07:00
Tim Newsome 28eb10f43d Ensure the buffer doesn't overflow. 
Tested with a variety of prime buffer sizes.

Change-Id: I2b4835d46adf4c971111da88e8de4b46eb8dad41
 2017-10-04 15:23:38 -07:00
Tim Newsome abe7eba25a Merge pull request #118 from riscv/priv 
Fix priv access
 2017-10-04 12:52:21 -07:00
Tim Newsome 1b11d579ea Add read buffer to bitbang, improving performance. 
This reduces the time for one testcase where OpenOCD connects to a
simulator from 12.30s to 5.35s!

Running all our tests went from 13m13s to 3m55s.

Change-Id: I7dc774e1e0f5752905ac4318fd9b85b930374a05
 2017-10-03 15:38:31 -07:00
Tim Newsome a3c26250bf Merge pull request #116 from riscv/multigdb 
Fix trigger code to work with multi-gdb mode instead of RTOS mode
 2017-10-03 11:53:58 -07:00
Tim Newsome e94c809ce4 Merge pull request #120 from gnu-mcu-eclipse/riscv-warnings 
Silence some clang warnings
 2017-10-03 11:27:57 -07:00
Tim Newsome 2f6dd2a4b5 Merge pull request #121 from gnu-mcu-eclipse/riscv-reorder 
flash/nor/Makefile.am: keep files in lexicographical order
 2017-10-03 11:26:32 -07:00
Liviu Ionescu 066ce338d8 flash/nor/Makefile.am: lexicographical order 2017-10-03 00:48:15 +03:00