Commit Graph

10733 Commits

Author SHA1 Message Date
Erhan Kurubas d59bf1d96a flash: fix clang static analyzer build errors
Fixes "variable set but not used" errors.
Tested with Homebrew clang version 13.0.1

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ia90baf5b4857db2b5569ebe6adbbb832de772aad
Reviewed-on: https://review.openocd.org/c/openocd/+/6971
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-12-14 15:32:13 -08:00
Tim Newsome f7a5f4719d
Merge pull request #772 from riscv/resume_state
target/riscv: Set target->state in riscv013_halt_go()
2022-11-30 10:21:24 -08:00
Tim Newsome 86e84d3f6d target/riscv: Set target->state in riscv013_halt_go()
Then also set it when we resume in examine(), which doesn't use the full
abstractions because not all required data structures are filled out
yet.

Hopefully fixes #749.

Change-Id: I0c6ab16da1f035ca2fbdb9f7be1462d44ddce3a0
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-29 09:24:24 -08:00
Tim Newsome d6bf022560
Merge pull request #767 from riscv/unavailable
Handle harts becoming unavailable while they're being debugged.
2022-11-25 10:18:12 -08:00
Tim Newsome 2d7dc3f5f5 target/riscv: Fix small riscv013_halt_go() bug
Exit the loop when no harts are running, instead of when at least one
hart has halted.

Change-Id: Ia69b626bf1fee4034bd5ccc800a651bfe0e53685
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 13:00:01 -08:00
Tim Newsome 69222be761 target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAK
Simple rename to make code slightly more clear.

Change-Id: I959f83164c55de064d902d4e5bcd49333cef5c91
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 13:00:01 -08:00
Tim Newsome bf15b00315 target/riscv: Set correct target->state in riscv013_halt_go()
It used to set all states to halted, but that's not right for harts that
are now unavailable. (It might be possible to call poll() at the right
time instead of duplicating some of its code, but I didn't see an easy
way to do that. The real requirement is that target->state is set to
TARGET_UNAVAILABLE before TARGET_EVENT_HALTED is is sent in
halt_finish(), because that's what triggers hwthread_update_threads(),
which must know about unavailable harts so they can be hidden from gdb.

Change-Id: I0a0bbdd4ec9ff8c9898e04045b84e1d2512c9336
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 12:59:58 -08:00
Tim Newsome e69735db0b gdb_server: Operate on available targets.
When SMP is enabled, gdb will always use the first target in the SMP
group. That doesn't work when that first target is unavailable, but
others in the SMP group are still available.

For cases where gdb expects an operation to affect the entire group (run
control, memory access), find the first available target in an SMP group
and use that.

Change-Id: I4bed600da3ac0fdfe4287d8fdd090a58452db501
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome b1f3a75819 target/riscv: Don't resume unavailable harts.
Change-Id: I30a2e9ec6c1b99fb92ab1a160ddb63682167c6d8
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome d3bffe3d86 target/riscv: Share single-target and SMP resume code.
Change-Id: I416d8cc4c8c5ca0337c1f7e392b6b4fa3d75757f
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome 5832b983f5 rtos/hwthread: Hide unavailable targets from thread list.
Change-Id: I53c6e2876d9bab70800a0f080e72a2abe0499120
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome ad93fda7e8 target/riscv: Make poll() use TARGET_UNAVAILABLE.
Change-Id: I7052dd08581f0ce6a05cd8319e9bec0086296fc3
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:47 -08:00
Tim Newsome e5f9024bb0 target/riscv: Refactor riscv_openocd_poll()
There used to be entirely separate code paths depending on whether we're
in SMP mode or not. Now they're both the same.

Change-Id: I8f46295e4bc005f441af0c03d4f608c53b8a6586
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21 10:26:21 -08:00
Tim Newsome 5a48975118 target/riscv: Error when hart becomes unavailable during resume
Change-Id: I731e6178b2b08b65206614b0dc2a0d993c149cc3
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21 10:26:21 -08:00
Tim Newsome cc5e78172a
Merge pull request #769 from riscv/0.11
Revive 0.11 debug spec support
2022-11-21 09:26:38 -08:00
Tim Newsome f1e20767bc target/riscv: 0.11, call handle_halt() after step
This ensures that we populate the register cache and set target->state.
Some RISC-V changes had upset the balance.

Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17 11:41:27 -08:00
Tim Newsome e16d7a5611 target/riscv: Ignore maskmax when reading back tdata1
We don't correctly write it, so we shouldn't expect it to read back the
same value. Fixes hardware breakpoints on mcontrol triggers.

Change-Id: Ie5e445060ec9c8887af933fd8887e57308330f09
2022-11-17 11:41:24 -08:00
Tim Newsome bec0fe2236
target/riscv: Don't always read on DMI batch write (#768)
Indicate to the JTAG driver that it does not need
to read and return the DR register value after scanning the
JTAG chain.

riscv_batch_run(), calls jtag_add_dr_scan() to schedule a
DR scan operation. Eventually, this will result in the JTAG
driver performing a JTAG scan to write to or read from DR.
The decision on whether to write to and/or read from DR
register is determined by the second parameter to
jtag_add_dr_scan(), i.e. a "struct scan_field".
Of particular interest here is if
batch->fields[i]->in_value is not NULL, the JTAG developer
must return the DR value collected from the JTAG  scan
operation.

When creating the DR scan operation instruction with
riscv_batch_add_dmi_write(), batch->fields[i]->in_value points
to a location in batch->data_in buffer,
meaning batch->field[i]->in_value is not NULL, and the JTAG
developer must therefore read and return the DR value collected.
The returning of the DR value is redundant in a write
operation.

This patch set batch->fields[i]->in_value to NULL to indicate
the DR value need not be returned. This allows the JTAG
developer to optimize away any code associated with returning
the DR value.

Normally, the extra work to return the DR value is negligible.
However, in one usecase it introduces significant delays
In this use case a JTAG driver forwards
all JTAG scan to a server on a network. If the server has to
return the DR value, it has to perform the JTAG scan before
replying to the JTAG driver, and only then the JTAG driver
can send the next JTAG scan operation. However, if there is
no need to return the DR value, the server can
acknowledge the JTAG operation request immediately,thus
signalling  to the JTAG driver that it is free to send the next
JTAG scan operation. At the same time of receiving the second
JTAG operation the server will process the original JTAG scan.
This saves time and mitigates network delay. Also, not having
to include the DR value in resulting in smaller reply packet
from server to JTAG driver and save on network traffic.

This doubles download speeds to spike using remote bitbang.

Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
2022-11-17 11:34:27 -08:00
Tim Newsome fc210e8689 target/riscv: Ignore debug_execution in 0.11 resume
It's only used to change what callback events are generated, and there
are none anyway. (That's probably a bug, but since 0.11 is so rare I'm
not going to worry about it.)

Fixes #757.

Change-Id: I5b5df3a9bec927fb0368304229533e2875a83f6b
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17 09:49:28 -08:00
Evgeniy Naydanov 8ae41e86e1
Fix breackpoint_add for rtos swbp (#734)
breakpoint_add should use rtos only if request is done by gdb.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I779d1a905c6a3640869dca162e3cc001919e8f42

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-16 11:03:43 -08:00
Evgeniy Naydanov dc49ed8ae2
Workaround for fp register access in case fp unit is disabled (#766)
On some boards there is a HW bug: if fp unit is disabled (fs in mstatus
set to 0), accessing any fp register results in a hang (any abstract
command timeouts, untill the board is rebooted).

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I0c0d1033889f15dcc326c4078bf9cbb5a8558565

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-15 08:52:13 -08:00
Tim Newsome 57dbcb1d02
Improve a couple of user/debug messages. (#763)
* gdb_server: Improve info message.

Add target name and state to "Not running when halt was requested"
message.

Change-Id: Ic84e9a884b57caa270cfee0ca6fa6a0dd8e5d2bd
Signed-off-by: Tim Newsome <tim@sifive.com>

* rtos/hwthread: Nicer debug message in hwthread_update_threads()

Change-Id: Ia5931a772476a2ae186ed87cd70d7e4be2f196fb
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10 10:32:23 -08:00
Tim Newsome f59bb72fde
target/riscv: Use vlenb to check whether vector registers exist (#762)
E.g. the Zve* vector extensions have all the same registers as the full
V extension, but leaves misa.V clear.

Change-Id: Ib08c3612c52bb3a6b074d9431e3396c8f2f0ff27
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10 10:27:46 -08:00
Tim Newsome 88a629c017
riscv/target: Replace is_halted() with get_hart_state() (#756)
Prep work for handling unavailable harts.

Change-Id: I9c00ed4cdad8edeaa5a13fbec7f88f40d8af9028
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10 10:27:04 -08:00
Xiang W 61f183fb25
Use match field for trigger (#725)
* Use match field for trigger

The watchpoint cannot capture all data modifications only through the
trigger of ANY SIZE and EQUAL, and an error will occur. This patch
accommodates watchpoints by adding more types of matches

Change-Id: I5c3c908dbd49ca47755b06f5cdbe451be3a81c8b
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Change-Id: I3670347c4b00bf508373f7cc2f4950cbc09d6e2a
Signed-off-by: Xiang W <wxjstz@126.com>

* Add variable type trigger support

Change-Id: I60922c5f98574040b9a160e2aa0355871a581fe1
Signed-off-by: Xiang W <wxjstz@126.com>

* remove trailing whitespace

Change-Id: I168812e12b459ae3c4b3017c27a9b897e65d9f84
Signed-off-by: Xiang W <wxjstz@126.com>

* update triggers enumerate

Change-Id: I23a66afb0f772934b8911b522d0e4f116917519f
Signed-off-by: Xiang W <wxjstz@126.com>

Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09 14:48:31 -08:00
Tim Newsome ae3ad22311
target/riscv: Deal with DMI busy in sample_memory_bus_v1() (#758)
* target/riscv: Deal with DMI busy in sample_memory_bus_v1()

Change-Id: I810a4c4b7f02cb40ea99b7a500dce23c1bbd9231
Signed-off-by: Tim Newsome <tim@sifive.com>

* Comment code more clearly.

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Remove extra tab

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09 14:39:19 -08:00
Dolu1990 70980e7f57
Fix dm->current_hartid corruption on hartsellen discovery (#754)
* target/riscv Fix dm->current_hartid corruption on hartsellen discovery

Change-Id: Iec969df2675b608365eda2c3a83a4185752430f2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

* target/riscv Ensure HART_INDEX_DIRTY does not have side effects

Change-Id: Ie89c94d97cd4f15c1be0327fddff75beea6ae027
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
2022-11-01 09:51:33 -07:00
Tim Newsome cdadb2040b
github/workflow: enable libftdi based adapters (#755)
Change-Id: I74b07b21573294dd7d9d3caf41c5755622c77149
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7008
Tested-by: jenkins
Reviewed-by: Xiaofan Chen <xiaofanc@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-10-31 10:34:03 -07:00
Tim Newsome fad123a16b
target: Add TARGET_UNAVAILABLE state. (#752)
This is added for future RISC-V changes. The RISC-V debug interface can
explicitly tell a debugger when a hart is unavailable. This is used for
instance when that hart is powered down (or yet to be powered up out of
reset).

Change-Id: I8a062d59eea1e5b3c788281a75159592db024683
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-27 15:21:31 -07:00
Tim Newsome 9eb07f258e
target/riscv: Correctly set target->state in deassert_reset (#750)
* target/riscv: Correctly set target->state in deassert_reset

This bug didn't lead to problems, but it would with some upcoming
changes.

Change-Id: I552acbae9977150c4c9e573f8852033bc80fcebb
Signed-off-by: Tim Newsome <tim@sifive.com>

* Keep debug_reason in sync with state

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-21 09:16:54 -07:00
Anatoly Parshintsev fe5c7d7a35
[riscv] step operation handler should respect handle_breakpoints parameter (#741)
* [riscv] step operation handler should respect handle_breakpoints parameter

When step operation is requested the OpenOCD frontend (like gdb server
or TCL server) has an option to control how existing breakpoints are
handled upon step.

Some OpenOCD frontends (like gdbserver) may choose to disable special
handling of existing breakpoints - thus handle_breakpoints is set to 0,
while others (like TCL server) expect target handler to temporary
disable the matching breakpoint to allow the step operation to complete
successfully.

In the current implementation handle_breakpoints parameter was ignored
by target-specific handler. Thus, the following sequence of commands:

```
halt
bp <current_pc> 4
step
```

Resulted in *step* operation to not change PC because of bp match.

This commit addresses this issue.

* Adjusted calls to logging facilities (addressed review comments)

Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>

Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
2022-10-14 09:40:16 -07:00
Tim Newsome a50b280558
Properly track selecting multiple harts at once. (#743)
* Properly track selecting multiple harts at once.

use_hasel is a bit of a hack.

Change-Id: Ia589ebc16bca32038d915df9988361b88e940917
Signed-off-by: Tim Newsome <tim@sifive.com>

* Clarifying comment.

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Rename set_hartsel to set_dmcontrol_hartsel

Change-Id: Iab28531281aa6fc604ec7d34974ed444ea9ea850

* Make set_dmcontrol_hartsel() more idiomatic.

Change-Id: I56a885043c515359e33b9c8a03aed637c81d1486

* Use constant for multiple harts instead of -1.

Change-Id: Iefeaf74202f2b4918d21f15f7ff7ca514175b8fb
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-12 08:57:00 -07:00
Tim Newsome bed28d5ec7 filter_openocd: Prefer high repetitions.
I'd rather see "these 10 lines were repeated 100 times" than "these 100
lines were repeated 10 times."

Change-Id: I88fcf86b10c5fb0ba1d19b21fe054065da90fedd
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-12 08:53:50 -07:00
Tim Newsome 4270857a76 target/riscv: Clean up halt_go for multiple harts.
Also add an early exit for if any harts are unavailable.

Change-Id: I0875d4d213c9faf87b219d8d57e440881366c8f8
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-11 13:57:55 -07:00
Tim Newsome 51aa8053e2
Merge pull request #745 from dmitryryzhov/fix-braces
Fix incorrect braces caused by #732
2022-10-10 09:51:12 -07:00
Tim Newsome f6163aacb4
Merge pull request #744 from mrv96/cjtag
Handle correctly cJTAG reset
2022-10-10 09:43:11 -07:00
mrv96 0c6121d92a (Re)Init cJTAG before move JTAG to reset state
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-10-07 16:07:33 +02:00
mrv96 29983fd98d (Re)Init cJTAG only after trst (not after srst) 2022-10-07 15:47:44 +02:00
Dmitry Ryzhov 01ae0f2122 Fix incorrect braces caused by #732 2022-10-07 16:34:59 +03:00
Tim Newsome b411a955c8
Merge pull request #742 from mrv96/cjtag
Fix Digilent JTAG-HS2 cJTAG configuration script
2022-10-06 09:43:11 -07:00
mrv96 342ca4a832 Fix Digilent JTAG-HS2 cJTAG configuration script
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-10-05 19:42:15 +02:00
Tim Newsome 0f12a01007 riscv: Minor formatting cleanup.
Change-Id: I0256fd047d8369ca7b327172225a9d1f827673c5
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-05 10:23:45 -07:00
mrv96 088a3596a0 Use TMSC_EN signal for cJTAG escape seq if defined
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-10-05 10:16:53 -07:00
mrv96 bd5649dfbe Support cJTAG JScan3 mode 2022-10-05 10:16:53 -07:00
mrv96 f61098c225 Rename ftdi_oscan1 to ftdi_cjtag 2022-10-05 10:16:53 -07:00
mrv96 b70ccf297f OScan1 code cleanup
- change OSCAN1 to OScan1
- fix spacing
2022-10-05 10:16:53 -07:00
Tim Newsome 6d4ba7cca8
Merge pull request #738 from riscv/current_hartid
Remove riscv_info_t.current_hartid
2022-10-04 13:17:59 -07:00
Tim Newsome 84365e65e5 Remove riscv_info_t.current_hartid
This was used to track which hart a given operation must apply to. But
we already have a target associated with each operation, and from there
we can find the desired hart id. dm013_info_t already tracks
current_hartid (meaning which hart ID is currently selected by the DM).

This makes the code simpler to understand. Also it turns out we don't
need to make sure the correct hart ID is currently selected because
there are only a few real entry points.

Change-Id: Ibe8d5e156523397f245edd6ec0a5df3239b717bf
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-30 10:21:38 -07:00
Tim Newsome 550a66e720
Use LOG_TARGET_FOO() functions in more places. (#731)
Change-Id: Id2266dbfb6209bf0676f28e7383a12705ce2a70e
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-29 15:09:49 -07:00
Tim Newsome 23df83e830
Merge pull request #727 from riscv/poll_backoff
Make poll backoff time based.
2022-09-27 10:13:12 -07:00