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ethernet
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WIP 100BASE-TX PHY
72 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson cf0aed4980 pmd_io: Rename to pmd_dp83223_rx 
This better reflects that this is an interface intended to be used with
the DP83223. While we're at it, refactor the module to just handle the
the recieve portion.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-10-30 22:01:35 -04:00
rtl pmd_io: Rename to pmd_dp83223_rx 2022-10-30 22:01:35 -04:00
tb pmd_io: Rename to pmd_dp83223_rx 2022-10-30 22:01:35 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Automatically dump signals 2022-10-30 14:20:48 -04:00