ethernet/rtl
Sean Anderson 7c9ac42988 Add wishbone mux
This adds a simple wishbone mux. The idea is that each slave gets its
own address bit. This lends itself to extemely simple address decoding,
but uses up address space quickly. In theory, we could also give larger
addres space to some slaves, but currently lower bits have priority. The
testbench is also very simple. Since everything is combinatorial, we can
determine the outputs from the inputs exactly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-02-18 22:48:36 -05:00
..
axis_mii_tx.v axis_mii_tx: Add support for half duplex 2023-01-14 00:08:38 -05:00
axis_replay_buffer.v Use separate process for non-resetting registers 2023-01-13 23:13:12 -05:00
common.vh Automatically dump signals 2022-10-30 14:20:48 -04:00
descramble.v descramble: Pass through scrambled_valid 2022-11-05 11:54:39 -04:00
hub_core.v Silence warnings when converting memories to registers 2023-02-18 22:48:36 -05:00
io.vh Add pmd 2022-08-06 14:02:44 -04:00
iverilog_dump.v Automatically dump signals 2022-10-30 14:20:48 -04:00
led_blinker.v Add LED blinker 2023-02-18 22:48:36 -05:00
mdio.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_io.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_regs.v pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
mii_elastic_buffer.v mii_elastic_buffer: Don't use memory access hack on valid/err 2023-02-18 22:48:36 -05:00
mii_io_rx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mii_io_tx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
nrzi_decode.v nrzi_decode: Add reset input 2022-11-30 18:14:23 -05:00
nrzi_encode.v Automatically dump signals 2022-10-30 14:20:48 -04:00
pcs.vh pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
pcs_rx.v pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
pcs_tx.v pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
phy_core.v phy_core: Simplify collision logic 2022-11-30 18:14:23 -05:00
pmd_dp83223.v Add DP83223-based PMD 2022-11-30 18:14:23 -05:00
pmd_dp83223_rx.v pmd: Initialize sd_delay 2023-01-09 20:31:39 -05:00
scramble.v scramble: Fix initial lfsr value 2023-01-09 20:51:59 -05:00
wb_mux.v Add wishbone mux 2023-02-18 22:48:36 -05:00