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ethernet
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WIP 100BASE-TX PHY
76 Commits 2 Branches 0 Tags 285 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson 7d35e07401 mdio_regs: Add support for counters 
This adds support for counters for interesting conditions (disconnects,
PMD phase wraparounds, errors, etc). All the counters are 15 bits
instead of 16, because 16-bit counters have an fmax of 110MHz or so. All
the counters live behind a condition because they ~double the number of
resources used.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-11-02 17:37:34 -04:00
rtl mdio_regs: Add support for counters 2022-11-02 17:37:34 -04:00
tb mdio_regs: Add support for counters 2022-11-02 17:37:34 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Automatically dump signals 2022-10-30 14:20:48 -04:00