skywater
/
ethernet
mirror of https://github.com/Forty-Bot/ethernet.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
WIP 100BASE-TX PHY
55 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
Go to file
Sean Anderson 67cf4100c6 descrambler: Break up locking logic 
This (un)locking logic was on the critical path. Break it up into
multiple parts to allow achieving our desired clock frequency.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-10-16 17:27:08 -04:00
rtl descrambler: Break up locking logic 2022-10-16 17:27:08 -04:00
tb Add MII management functions 2022-08-31 12:36:11 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Rename *post* targets to *synth* 2022-09-04 17:14:45 -04:00