descrambler: Break up locking logic
This (un)locking logic was on the critical path. Break it up into multiple parts to allow achieving our desired clock frequency. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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@ -13,7 +13,8 @@ module descramble (
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output reg [1:0] unscrambled, unscrambled_valid
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);
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reg locked_next;
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reg relock, relock_next, locked_next;
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initial relock = 0;
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reg [1:0] ldd, unscrambled_next;
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reg [10:0] lfsr, lfsr_next;
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@ -73,15 +74,20 @@ module descramble (
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idle_counter_next = CONSECUTIVE_IDLES;
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end
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locked_next = 1;
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unlock_counter_next = unlock_counter;
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relock_next = 0;
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if (!idle_counter_next[4:1]) begin
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unlock_counter_next = test_mode ? TEST_UNLOCK_TIME : UNLOCK_TIME;
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/*
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* Reset the counter to 2 to ensure we can always
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* subtract idles without underflowing
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*/
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idle_counter_next = 2;
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relock_next = 1;
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end
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locked_next = 1;
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unlock_counter_next = unlock_counter;
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if (relock) begin
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unlock_counter_next = test_mode ? TEST_UNLOCK_TIME : UNLOCK_TIME;
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end else if (|unlock_counter) begin
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unlock_counter_next = unlock_counter - 1;
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end else begin
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@ -94,12 +100,14 @@ module descramble (
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if (signal_status) begin
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lfsr <= lfsr_next;
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idle_counter <= idle_counter_next;
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relock <= relock_next;
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unlock_counter <= unlock_counter_next;
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locked <= locked_next;
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unscrambled_valid <= scrambled_valid;
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end else begin
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lfsr <= 0;
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idle_counter <= CONSECUTIVE_IDLES;
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relock <= 0;
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unlock_counter <= 0;
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locked <= 0;
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unscrambled_valid <= 0;
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