ethernet/tb
Sean Anderson 16b639aad2 Add MII elastic buffer
In order to move data between MIIs without implementing a MAC, we need
some kind of elastic buffer to bring the data into the transmit "clock
(enable) domain." Implement one. It's based on a classic shift-register
FIFO, with the main difference being the MII interfaces and the
elasticity (achieved by delaying asserting RX_DV until we reach the
WATERMARK). We use a register-based buffer because we only need to deal
with an under-/over-flow of 5 or so clocks for a 2000-byte packet. The
per-stage resource increase works out to 6 FFs and 1 LUT, which is
pretty much optimal.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-02-12 19:53:44 -05:00
..
__init__.py Make testbenches a module 2022-08-21 12:36:28 -04:00
axis_mii_tx.py axis_mii_tx: Add support for half duplex 2023-01-14 00:08:38 -05:00
axis_replay_buffer.py tb: Fix reset occasionally failing 2023-01-14 00:05:35 -05:00
descramble.py descrambler: Rename unscrambled* to descrambled* 2022-10-16 18:53:47 -04:00
hub_core.py Add a basic hub 2023-01-21 17:39:25 -05:00
mdio.py mdio: Support 2022-08-29 21:25:25 -04:00
mdio_io.py mdio:io: Don't drive mdio as X in testbench 2022-10-16 17:37:38 -04:00
mdio_regs.py pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
mii_elastic_buffer.py Add MII elastic buffer 2023-02-12 19:53:44 -05:00
mii_io_rx.py mii_io: Add isolation support 2022-08-28 18:43:23 -04:00
mii_io_tx.py mii_io: Add isolation support 2022-08-28 18:43:23 -04:00
nrzi_decode.py nrzi_decode: Add reset input 2022-11-30 18:14:23 -05:00
nrzi_encode.py nrzi_encode: Fix test name 2022-11-05 12:37:18 -04:00
pcs.py pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
pcs_rx.py tb: pcs_rx: Allow err to be optional 2023-01-09 21:02:35 -05:00
pcs_tx.py Add phy_core 2022-11-05 12:37:18 -04:00
phy_core.py tb: phy_core: Fix col/crs detection 2023-01-09 20:50:00 -05:00
pmd_dp83223.py Add DP83223-based PMD 2022-11-30 18:14:23 -05:00
pmd_dp83223_rx.py pmd: Export check_bits from testbench 2023-01-09 20:38:52 -05:00
scramble.py Add phy_core 2022-11-05 12:37:18 -04:00
util.py Add AXI stream replay buffer 2022-11-30 18:14:23 -05:00