ethernet/rtl
Sean Anderson 11bb9651c0 Use separate process for non-resetting registers
Including registers which are not reset in an asynchronous reset process
causes active-low clock-enable flip-flops to be synthesized. This is an
unusual configuration, incurs overhead, and isn't what we wanted to do
anyway. Use a separate process.

While we're at it, sort the bottom half of the if to match the top.

Fixes: 19f2f65 ("axis_mii_tx: Add reset")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-01-13 23:13:12 -05:00
..
axis_mii_tx.v Use separate process for non-resetting registers 2023-01-13 23:13:12 -05:00
axis_replay_buffer.v Use separate process for non-resetting registers 2023-01-13 23:13:12 -05:00
common.vh Automatically dump signals 2022-10-30 14:20:48 -04:00
descramble.v descramble: Pass through scrambled_valid 2022-11-05 11:54:39 -04:00
io.vh Add pmd 2022-08-06 14:02:44 -04:00
iverilog_dump.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_io.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_regs.v pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
mii_io_rx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mii_io_tx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
nrzi_decode.v nrzi_decode: Add reset input 2022-11-30 18:14:23 -05:00
nrzi_encode.v Automatically dump signals 2022-10-30 14:20:48 -04:00
pcs.vh pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
pcs_rx.v pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
pcs_tx.v pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
phy_core.v phy_core: Simplify collision logic 2022-11-30 18:14:23 -05:00
pmd_dp83223.v Add DP83223-based PMD 2022-11-30 18:14:23 -05:00
pmd_dp83223_rx.v pmd: Initialize sd_delay 2023-01-09 20:31:39 -05:00
scramble.v scramble: Fix initial lfsr value 2023-01-09 20:51:59 -05:00