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ethernet
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WIP 100BASE-TX PHY
79 Commits 2 Branches 0 Tags 285 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson 02069bceee pcs: Add false_carrier signal 
This adds an explicit false carrier signal. Trying to determine this
condition the MDIO signals is tricky because BAD_SSD can last over
several cycles of CE. To make things easier, add a signal which is high
only once per event.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-11-05 12:37:18 -04:00
rtl pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
tb pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Automatically dump signals 2022-10-30 14:20:48 -04:00