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ethernet
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Author SHA1 Message Date
Sean Anderson 897326dbdb Move default_nettype/timescale declaration to common.vh 
We will need this in every verilog file, so consolidate things a bit. In
terms of timescale, we need to modify the post-synthesis verilog
generation a bit in order to avoid the module's timecale being
inadverdently overwritten.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2022-08-24 12:04:10 -04:00
Sean Anderson 6ffb3481fe Add post-synthesis simulation support 
This adds support for running testbenches post-synethesis. Simulating
this way should (hopefully) catch most synthesis/simulation mismatches.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2022-08-06 21:47:21 -04:00
Sean Anderson d351291ff8 Initial commit 2022-05-23 20:57:03 -04:00