Commit Graph

5 Commits

Author SHA1 Message Date
Sean Anderson 86aee33477 Use MODULE variable for tests
Instead of listing out tested modules each time, use a variable.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:10:07 -04:00
Sean Anderson 50c1080ba4 Support colorized output with -O
Using -O allows grouping job output, which is helpful when output would
otherwise be interleaved (such as when running tests). However, it also
means that there is no tty attached to the job, resulting in cocotb
automatically turning off color. Detect whether we have a tty during the
parsing phase, and force color output if we do. Technically this should
probably take into account the existing value of COCOTB_ANSI_OUTPUT, but
I don't use it normally.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:07:25 -04:00
Sean Anderson 897326dbdb Move default_nettype/timescale declaration to common.vh
We will need this in every verilog file, so consolidate things a bit. In
terms of timescale, we need to modify the post-synthesis verilog
generation a bit in order to avoid the module's timecale being
inadverdently overwritten.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:04:10 -04:00
Sean Anderson 6ffb3481fe Add post-synthesis simulation support
This adds support for running testbenches post-synethesis. Simulating
this way should (hopefully) catch most synthesis/simulation mismatches.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 21:47:21 -04:00
Sean Anderson d351291ff8 Initial commit 2022-05-23 20:57:03 -04:00