Commit Graph

62 Commits

Author SHA1 Message Date
Sean Anderson 897326dbdb Move default_nettype/timescale declaration to common.vh
We will need this in every verilog file, so consolidate things a bit. In
terms of timescale, we need to modify the post-synthesis verilog
generation a bit in order to avoid the module's timecale being
inadverdently overwritten.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:04:10 -04:00
Sean Anderson 03715d4a83 pcs: rx: Only flush on state change
The PCS state machine is evaluated every cycle, but its outputs are only
registers when the rx_bits module indicates. However, the flush signal
is not registered and is instead combinatorial. Although it's OK to
evaluate the other outputs every cycle, we should only indicate if we
are actually going to change state.

Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 22:08:09 -04:00
Sean Anderson 6d7847c35f common: Add levels parameter to DUMP
This adds a levels parameter to DUMP, allowing dumping just the
top-level signals, instead of the whole hierarchy. This is helpful for
post-synthesis simulation, where all sub-modules are primitives (with
their inputs and outputs already available at the top level).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 21:47:21 -04:00
Sean Anderson 8f7c797800 pcs: Fix incorrect assignment type
This is the wrong kind of assignment to use. Fix it.

Fixes: 1d65661 ("Add pmd")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 21:47:21 -04:00
Sean Anderson d8ce1652ae pmd: Delay signal_status/detect until data is valid
The data yielded by the PMD is not really valid until it has made its
way through the pipeline. Delay it until the data is valid. As a side
effect, this should also eliminate any metastability. This is not
necessary for real hardware, but it allows us to to post-synthesis
simulation (where we can't reach in and probe the internal valid
signal).

Additionally, ensure that the state is known by resetting it when we
don't have a signal.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 21:47:21 -04:00
Sean Anderson fafce4df00 pmd: Use correct SB_IO clock names
The clock signals are not named correctly. Fix this.

Fixes: 1d65661 ("Add pmd")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 21:47:21 -04:00
Sean Anderson 93e91e3eb0 pcs: Fix some lint
There were two unused variables; remove them. The wrong type of
assignments were used; fix them.

Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 15:21:15 -04:00
Sean Anderson d2b4f9b061 pcs: rx: Add premature end state
Without this state, receiving would immediately go low. However, figure
24-11 shows that receiving should go low only after an additional code
group (the second idle) is received.

Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 15:18:26 -04:00
Sean Anderson e4bbc08620 pcs: tx: Calculate idle correctly when there is no new data
When the PMA has no new data for us, idle should be determined based on
raw_bits[11:2]. However, we just calculated that last cycle, so we can
reuse it.

Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 14:54:04 -04:00
Sean Anderson 0dea0304af pcs: tx: Process link failure synchronously
There's no strict requirement for us to handle linke failures immediately.
The PMA's link timer will ensure the signal stays low, so we don't have to
worry about missing it. This fixes some strange Xs during initialization.

Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 14:51:23 -04:00
Sean Anderson 1d65661bd3 Add pmd 2022-08-06 14:02:44 -04:00
Sean Anderson d351291ff8 Initial commit 2022-05-23 20:57:03 -04:00