riscv

riscv synced commits to claire/fix2728 at riscv/yosys from mirror 2021-06-17 22:49:03 -05:00

0d6f052893 Re-enable opt_dff_sr equiv_opt checks

7fbb320042 Add "check -assert" to equiv_opt

43958ee548 Add equiv_opt -neghold -negsetup -simple

9d20ed18a8 Exclude primary inputs from quiv_make rewiring

daace6b154 Add clk2fflogic -negsetup

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riscv synced commits to devel at riscv/coriolis from mirror 2021-06-17 19:19:05 -05:00

72b5de88c4 Fix bugs in AutoSegment::isMiddleStack() and canReduce().

ddc7aef13b At last make use of cdebug_log() in Track::repair().

f873e616cb Use of tset() manipulator instead of setw() when printing in cdebug_log.

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riscv synced commits to master at riscv/yosys from mirror 2021-06-16 22:19:03 -05:00

e2c9580024 Move interface expansion in hierarchy.cc into a helper class

f2c2d73f36 sv: fix up end label checking

092f0cb01e Include blif reader header in public facing extension header files.

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riscv synced commits to develop at riscv/caravel from mirror 2021-06-16 15:09:03 -05:00

202feaf50c Apply automatic changes to Manifest and README.rst

07ae0b060f [RTL] rtl updates

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riscv synced commits to mpw-one-final-metal-fix at riscv/caravel from mirror 2021-06-16 15:09:03 -05:00

d61bd89ac8 Update chip_io split netlist

19a12ee7bb Apply automatic changes to Manifest and README.rst

4e349267e7 updated the RTL/GL/SB to include the _pad ports for power

8dd15a79e7 1) create ./lvs directory

f8aa2320c2 added updated gl chip_io.v that matches the chip_io.mag on this commit

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riscv synced commits to gatecat/pyosys-sigint at riscv/yosys from mirror 2021-06-16 14:19:02 -05:00

riscv synced new reference gatecat/pyosys-sigint to riscv/yosys from mirror 2021-06-16 14:19:02 -05:00

riscv synced new reference verific_command to riscv/yosys from mirror 2021-06-16 06:19:03 -05:00

riscv synced commits to sanitizers at riscv/yosys from mirror 2021-06-16 06:19:02 -05:00

riscv synced new reference sanitizers to riscv/yosys from mirror 2021-06-16 06:19:02 -05:00

riscv synced commits to verific_command at riscv/yosys from mirror 2021-06-16 06:19:02 -05:00

riscv synced commits to master at riscv/yosys from mirror 2021-06-14 14:19:03 -05:00

c6681508f1 verilog: fix leaking of type names in parser

b57e47fad8 verilog: fix wildcard port connections leaking memory

62a42c317c ast: delete wires and localparams after finishing const evaluation

091295a5a5 verilog: fix leaking ASTNodes

9ca5a91724 ast: fix error condition causing assert to fail

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riscv synced commits to master at riscv/yosys from mirror 2021-06-11 06:09:03 -05:00

438bcc68c0 Add regression test for #2824.

6a6d049f1c opt_muxtree: Update port_off and port_idx even for constant bits

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riscv synced and deleted reference claire/fixemails at riscv/yosys from mirror 2021-06-09 13:49:03 -05:00

riscv synced commits to master at riscv/yosys from mirror 2021-06-09 13:49:03 -05:00

1667ad658b opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.

12b3a9765d opt_expr: Optimize div/mod by const 1.

55e8f5061a Merge pull request #2817 from YosysHQ/claire/fixemails

588137cd08 Fix deadname SVN links

2d95a7da9c Intersynth URL

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riscv synced commits to claire/fixemails at riscv/yosys from mirror 2021-06-09 05:39:03 -05:00

a734face3a More deadname stuff

0ada13cbe2 Use HTTPS for website links, gatecat email

92e705cb51 Fix files with CRLF line endings

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riscv synced commits to master at riscv/yosys from mirror 2021-06-08 21:39:02 -05:00

2e697f5655 verilog: check for module scope identifiers during width detection

c79fbfe0a1 mem2reg: tolerate out of bounds constant accesses

d9f11bb7a6 autoname: simple perf optimizations

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riscv synced commits to claire/fixemails at riscv/yosys from mirror 2021-06-07 21:29:03 -05:00

riscv synced new reference claire/fixemails to riscv/yosys from mirror 2021-06-07 21:29:03 -05:00

riscv synced commits to libera-JVNl9jWSzau4FgBX at riscv/yosys from mirror 2021-06-01 17:29:02 -05:00