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verilog: fix wildcard port connections leaking memory

This commit is contained in:
Xiretza 2021-03-18 10:38:36 +01:00 committed by Zachary Snow
parent 62a42c317c
commit b57e47fad8
1 changed files with 1 additions and 0 deletions
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frontends/verilog/verilog_parser.y
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@ -2084,6 +2084,7 @@ cell_port:
if (!sv_mode)
frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
free_attr($1);
};
always_comb_or_latch: