mirror of https://github.com/YosysHQ/yosys.git
verilog: fix wildcard port connections leaking memory
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@ -2084,6 +2084,7 @@ cell_port:
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if (!sv_mode)
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frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
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astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
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free_attr($1);
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};
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always_comb_or_latch:
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