Eddie Hung 27b7ffc754 ice40: fix ICESTORM_LC process sensitivity		2020-05-12 15:40:48 -07:00
..
tests	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
.gitignore	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
Makefile.inc	ice40: move over to specify blocks for -abc9	2020-02-27 10:17:29 -08:00
abc9_model.v	ice40: specify fixes	2020-02-27 10:17:29 -08:00
arith_map.v	ice40: reduce ABC9 internal fanout warnings with a param for CI->I3	2020-01-24 11:59:48 -08:00
brams.txt	ice40: match memory inference attribute values case insensitive.	2020-02-06 14:58:20 +00:00
brams_init.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
brams_map.v	ice40: use 2 bits for READ/WRITE MODE for SB_RAM map	2019-02-28 16:23:40 -08:00
cells_map.v	xilinx/ice40/ecp5: undo permuting LUT masks in lut_map	2020-01-27 13:30:27 -08:00
cells_sim.v	ice40: fix ICESTORM_LC process sensitivity	2020-05-12 15:40:48 -07:00
dsp_map.v	Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing	2019-08-08 12:56:05 -07:00
ice40_braminit.cc	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
ice40_ffinit.cc	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
ice40_ffssr.cc	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
ice40_opt.cc	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
latches_map.v	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
synth_ice40.cc	ice40: fix whitespace	2020-05-12 15:40:13 -07:00