riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/frontends/verilog
History
Clifford Wolf b56e06d2f5 Added support for verilog === operator 2013-05-07 14:35:40 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
const2ast.cc initial import 2013-01-05 11:13:26 +01:00
lexer.l Added support for verilog === operator 2013-05-07 14:35:40 +02:00
parser.y Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS) 2013-03-31 11:19:11 +02:00
preproc.cc initial import 2013-01-05 11:13:26 +01:00
verilog_frontend.cc Implemented proper handling of stub placeholder modules 2013-03-28 09:20:10 +01:00
verilog_frontend.h initial import 2013-01-05 11:13:26 +01:00