yosys/passes
Jannis Harder f7023d06a2 sim: -hdlname option to preserve flattened hierarchy in sim output 2022-08-16 13:37:30 +02:00
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cmds rename: Add -witness mode 2022-08-16 13:37:30 +02:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Add the $anyinit cell and the formalff pass 2022-08-16 13:37:30 +02:00
hierarchy Add the $anyinit cell and the formalff pass 2022-08-16 13:37:30 +02:00
memory memory_map: Add -formal option 2022-08-16 13:37:30 +02:00
opt wreduce: Keep more x-bits with -keepdc 2022-08-16 13:37:30 +02:00
pmgen Update comment 2022-02-02 03:21:09 +01:00
proc proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
sat sim: -hdlname option to preserve flattened hierarchy in sim output 2022-08-16 13:37:30 +02:00
techmap support file locations containing spaces 2022-08-08 20:30:50 +02:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00