yosys/tests/sim
N. Engelhardt 2de9f00368
Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing
2024-11-06 16:29:07 +01:00
..
tb test dlatchsr and adlatch 2022-02-16 13:58:51 +01:00
.gitignore
adff.v
adffe.v
adlatch.v
aldff.v
aldffe.v
assume_x_first_step.ys Assume x values for missing signal data in FST 2024-10-02 12:08:48 +02:00
dff.v
dffe.v
dffsr.v
dlatch.v
dlatchsr.v test dlatchsr and adlatch 2022-02-16 13:58:51 +01:00
run-test.sh Replace GNU specific invocation of basename(1) with the equivalent 2022-10-23 11:02:18 +13:00
sdff.v
sdffce.v
sdffe.v
sim_adff.ys
sim_adffe.ys
sim_adlatch.ys test dlatchsr and adlatch 2022-02-16 13:58:51 +01:00
sim_aldff.ys
sim_aldffe.ys
sim_dff.ys
sim_dffe.ys
sim_dffsr.ys
sim_dlatch.ys
sim_dlatchsr.ys test dlatchsr and adlatch 2022-02-16 13:58:51 +01:00
sim_sdff.ys
sim_sdffce.ys
sim_sdffe.ys
simple_assign.v Assume x values for missing signal data in FST 2024-10-02 12:08:48 +02:00
simple_assign.vcd Assume x values for missing signal data in FST 2024-10-02 12:08:48 +02:00
var_reference_with_whitespace.vcd Fix: handle VCD variable references with and without whitespace 2024-10-01 11:51:20 +02:00
var_reference_without_whitespace.vcd Fix: handle VCD variable references with and without whitespace 2024-10-01 11:51:20 +02:00
vcd_var_reference_whitespace.ys Fix: handle VCD variable references with and without whitespace 2024-10-01 11:51:20 +02:00
vector_assign.il Fix: handle VCD variable references with and without whitespace 2024-10-01 11:51:20 +02:00