mirror of https://github.com/YosysHQ/yosys.git
Assume x values for missing signal data in FST
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
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@ -258,7 +258,8 @@ void FstData::reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t sta
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std::string FstData::valueOf(fstHandle signal)
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{
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if (past_data.find(signal) == past_data.end())
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log_error("Signal id %d not found\n", (int)signal);
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if (past_data.find(signal) == past_data.end()) {
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return std::string(handle_to_var[signal].width, 'x');
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}
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return past_data[signal];
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}
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@ -0,0 +1,2 @@
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read_verilog simple_assign.v
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sim -r simple_assign.vcd -scope simple_assign
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@ -0,0 +1,8 @@
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module simple_assign (
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input wire in,
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output wire out
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);
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assign out = in;
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endmodule
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@ -0,0 +1,13 @@
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$version Yosys $end
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$scope module simple_assign $end
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$var wire 1 n2 in $end
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$var wire 1 n1 out $end
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$upscope $end
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$enddefinitions $end
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#0
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#5
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b1 n1
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b1 n2
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#10
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b0 n1
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b0 n2
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