Assume x values for missing signal data in FST

Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
This commit is contained in:
Roland Coeurjoly 2024-10-02 11:18:19 +02:00
parent 1bf908dea8
commit 5ea2c6e6e5
4 changed files with 26 additions and 2 deletions

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@ -258,7 +258,8 @@ void FstData::reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t sta
std::string FstData::valueOf(fstHandle signal)
{
if (past_data.find(signal) == past_data.end())
log_error("Signal id %d not found\n", (int)signal);
if (past_data.find(signal) == past_data.end()) {
return std::string(handle_to_var[signal].width, 'x');
}
return past_data[signal];
}

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@ -0,0 +1,2 @@
read_verilog simple_assign.v
sim -r simple_assign.vcd -scope simple_assign

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@ -0,0 +1,8 @@
module simple_assign (
input wire in,
output wire out
);
assign out = in;
endmodule

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@ -0,0 +1,13 @@
$version Yosys $end
$scope module simple_assign $end
$var wire 1 n2 in $end
$var wire 1 n1 out $end
$upscope $end
$enddefinitions $end
#0
#5
b1 n1
b1 n2
#10
b0 n1
b0 n2