yosys/techlibs/greenpak4
Andrew Zonenberg 634f18be96 extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos 2017-08-30 16:28:25 -07:00
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Makefile.inc Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass 2017-08-28 22:18:34 -07:00
cells_latch.v greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
cells_map.v extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos 2017-08-30 16:28:25 -07:00
cells_sim.v Fixed bug causing GP_SPI model to not synthesize 2017-08-27 07:31:48 -07:00
cells_sim_ams.v Moved GP_POR out of digital cells b/c it has delays 2017-08-14 10:45:39 -07:00
cells_sim_digital.v Fixed more issues with GreenPAK counter sim models 2017-08-15 09:18:36 -07:00
gp_dff.lib Fixed indenting in techlibs/greenpak4/gp_dff.lib 2016-03-29 13:44:14 +02:00
greenpak4_dffinv.cc greenpak4: Added support for inferred input/output inverters on latches 2016-12-10 19:58:32 +08:00
synth_greenpak4.cc extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos 2017-08-30 16:28:25 -07:00