mirror of https://github.com/YosysHQ/yosys.git
de79978372
* xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled |
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| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| intel_alm | ||
| sf2 | ||
| xilinx | ||
| .gitignore | ||