mirror of https://github.com/YosysHQ/yosys.git
d8f2a1fda0
write_cxxrtl: ignore disconnected module ports |
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.. | ||
aiger | ||
blif | ||
btor | ||
cxxrtl | ||
edif | ||
firrtl | ||
ilang | ||
intersynth | ||
json | ||
protobuf | ||
simplec | ||
smt2 | ||
smv | ||
spice | ||
table | ||
verilog |