yosys/techlibs/ecp5
Eddie Hung 8fbb55f4ab synth_*: no need to explicitly read +/abc9_model.v 2020-05-14 10:33:56 -07:00
..
tests
.gitignore
Makefile.inc Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init" 2020-05-14 10:33:56 -07:00
abc9_map.v
abc9_model.v
abc9_unmap.v
arith_map.v
brams.txt
brams_connect.py
brams_init.py
brams_map.v remove unused parameters 2020-03-06 16:45:36 +01:00
cells_bb.v ecp5: Add missing SERDES parameters 2020-05-12 21:12:26 +01:00
cells_ff.vh
cells_io.vh
cells_map.v Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init" 2020-05-14 10:33:56 -07:00
cells_sim.v ecp5: (* abc9_flop *) gated behind YOSYS 2020-05-14 10:33:56 -07:00
dsp_map.v ecp5: Force SIGNED ports to be 1 bit 2020-04-16 16:38:19 +01:00
ecp5_ffinit.cc Cleanup use of hard-coded default parameters in light of #1945 2020-04-22 12:02:30 -07:00
ecp5_gsr.cc ecp5: ecp5_gsr to skip cells that don't have GSR parameter again 2020-04-22 17:53:08 -07:00
latches_map.v
lutrams.txt
lutrams_map.v
synth_ecp5.cc synth_*: no need to explicitly read +/abc9_model.v 2020-05-14 10:33:56 -07:00