yosys/frontends
Eddie Hung dd5f206d9e verific: recover wiretype/enum attr as part of import_attributes() 2020-04-27 08:43:54 -07:00
..
aiger aigerparse: only define __STDC_FORMAT_MACROS it not already before. 2020-04-07 12:50:31 -07:00
ast ilang, ast: Store parameter order and default value information. 2020-04-21 19:09:00 +02:00
blif kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
ilang ilang, ast: Store parameter order and default value information. 2020-04-21 19:09:00 +02:00
json Update JSON front-end to process new attr/param encoding 2019-08-01 12:48:22 +02:00
liberty kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
rpc ast, rpc: record original name of $paramod\* as \hdlname attribute. 2020-04-18 03:47:28 +00:00
verific verific: recover wiretype/enum attr as part of import_attributes() 2020-04-27 08:43:54 -07:00
verilog Set Verilog source location for explicit blocks (`begin` ... `end`). 2020-04-17 06:23:03 +00:00