yosys/tests/arch
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
..
anlogic Simplify breaking tests/arch/*/fsm.ys tests 2020-03-20 11:25:17 -07:00
common ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 2020-02-06 16:52:51 +00:00
ecp5 Merge pull request #1603 from whitequark/ice40-ram_style 2020-04-10 14:51:01 +00:00
efinix Simplify breaking tests/arch/*/fsm.ys tests 2020-03-20 11:25:17 -07:00
gowin Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
ice40 Merge pull request #1603 from whitequark/ice40-ram_style 2020-04-10 14:51:01 +00:00
intel_alm synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
xilinx fix argument order for macOS compatibility 2020-03-18 15:11:49 +01:00
run-test.sh tests: extend tests/arch/run-tests.sh for defines 2020-03-05 08:08:32 -08:00