Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize		2019-08-01 17:27:34 +02:00
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Makefile.inc	anlogic: implement DRAM initialization	2018-12-20 07:56:15 +08:00
anlogic_determine_init.cc	Fix formatting for msys2 mingw build using GetSize	2019-08-01 17:27:34 +02:00
anlogic_eqn.cc	Fix formatting for msys2 mingw build using GetSize	2019-08-01 17:27:34 +02:00
arith_map.v	Initial support for Anlogic FPGA	2018-12-01 18:28:54 +01:00
cells_map.v	Merge pull request #750 from Icenowy/anlogic-ff-init	2019-01-02 15:52:22 +01:00
cells_sim.v	Fixed Anlogic simulation model	2019-01-25 19:25:25 +01:00
dram_init_16x4.vh	anlogic: implement DRAM initialization	2018-12-20 07:56:15 +08:00
drams.txt	anlogic: implement DRAM initialization	2018-12-20 07:56:15 +08:00
drams_map.v	anlogic: implement DRAM initialization	2018-12-20 07:56:15 +08:00
eagle_bb.v	Revert "Leave only real black box cells"	2018-12-17 23:20:40 +08:00
synth_anlogic.cc	Merge pull request #755 from Icenowy/anlogic-dram-init	2019-01-02 16:28:18 +01:00