yosys/passes
Clifford Wolf c80315cea4 Bugfix in hierarchy handling of blackbox module ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
..
cmds Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
equiv Fix equiv_simple, old behavior now available with "equiv_simple -short" 2017-04-28 18:57:53 +02:00
fsm Remove some dead code from fsm_map 2017-08-21 15:02:16 +02:00
hierarchy Bugfix in hierarchy handling of blackbox module ports 2018-01-05 13:28:45 +01:00
memory Typo fix. 2016-09-08 10:57:16 +03:00
opt Add warnings for driver-driver conflicts between FFs (and other cells) and constants 2017-12-12 17:13:27 +01:00
proc Add warnings for driver-driver conflicts between FFs (and other cells) and constants 2017-12-12 17:13:27 +01:00
sat Fix a bug in clk2fflogic memory handling 2017-12-14 03:05:55 +01:00
techmap Value of properties can be expression. 2018-01-03 21:37:17 +00:00
tests Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00