|
cmds
|
Add "add -mod"
|
2019-09-20 10:27:17 +02:00 |
|
equiv
|
Add equiv_opt -multiclock
|
2019-09-11 13:55:59 +01:00 |
|
fsm
|
RTLIL::S{0,1} -> State::S{0,1}
|
2019-08-07 11:12:38 -07:00 |
|
hierarchy
|
Adopt @cliffordwolf's suggestion
|
2019-09-03 12:18:50 -07:00 |
|
memory
|
stoi -> atoi
|
2019-08-07 11:09:17 -07:00 |
|
opt
|
Revert "SigSet<Cell*> to use stable compare class"
|
2019-09-13 09:49:15 -07:00 |
|
pmgen
|
Set [AB]CASCREG to legal values
|
2019-09-23 16:00:11 -07:00 |
|
proc
|
proc_clean: fix order of switch insertion.
|
2019-08-19 16:44:23 +00:00 |
|
sat
|
Revert "SigSet<Cell*> to use stable compare class"
|
2019-09-13 09:49:15 -07:00 |
|
techmap
|
Revert abc9.cc
|
2019-09-20 17:52:23 -07:00 |
|
tests
|
Document (* gentb_skip *) attr for test_autotb
|
2019-09-18 12:41:35 -07:00 |
e556d48d45