yosys/techlibs
Clifford Wolf 0c6ffc4c65 More fixes for bugs found using xsthammer 2013-06-13 11:18:45 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Added EXTRA_TARGETS Makefile variable 2013-03-28 16:53:40 +01:00
blackbox.sed initial import 2013-01-05 11:13:26 +01:00
simlib.v Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v 2013-04-07 16:42:29 +02:00
stdcells.v More fixes for bugs found using xsthammer 2013-06-13 11:18:45 +02:00
stdcells_sim.v initial import 2013-01-05 11:13:26 +01:00