yosys/kernel
Clifford Wolf edf11c635a Assert on new logic loops in "share" pass 2014-09-21 12:57:33 +02:00
..
bitpattern.h Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
calc.cc Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
celltypes.h Added $lcu cell type 2014-09-08 13:31:04 +02:00
consteval.h Simplified $fa undef model 2014-09-08 16:59:39 +02:00
driver.cc Added "synth" command 2014-09-14 16:09:06 +02:00
log.cc Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore 2014-08-23 15:14:58 +02:00
log.h Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore 2014-08-23 15:14:58 +02:00
macc.h Added the obvious optimizations to alumacc $macc generator 2014-09-15 12:22:03 +02:00
modtools.h Fixed build with gcc-4.6 2014-08-07 22:37:01 +02:00
register.cc Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
register.h Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
rtlil.cc Initialize RTLIL::Const from std::vector<bool> 2014-09-19 15:50:55 +02:00
rtlil.h Initialize RTLIL::Const from std::vector<bool> 2014-09-19 15:50:55 +02:00
satgen.h Simplified $fa undef model 2014-09-08 16:59:39 +02:00
sigtools.h Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
utils.h Assert on new logic loops in "share" pass 2014-09-21 12:57:33 +02:00
yosys.cc Create a default selection stack in RTLIL::Design::Design() 2014-09-02 22:49:24 +02:00
yosys.h Added new CodingReadme file (replaces CodingStyle and CHECKLISTS) 2014-09-16 11:26:44 +02:00